Re: [U-Boot] [PATCH 09/23] boston: Disable PCI bridge memory space alignment

[Bin Meng]

On Tue, Sep 27, 2016 at 2:29 AM, Paul Burton  wrote:
> On the MIPS Boston development board we have an Intel EG20T Platform
> Controller Hub connected to a Xilinx AXI to PCIe root port which is only
> assigned a 1MB memory region. The Intel EG20T contains a bridge device
> beneath which all of its peripheral devices can be found, and that
> bridge device contains a ROM. If we align to 1MB when we encounter each
> bridge device we therefore do something like this:
>
>   - Start with bus_lower at 0x1600.
>
>   - Find the Xilinx root bridge, which has no visible BARs so we do very
> little to it.
>
>   - Probe the bus beneath the Xilinx bridge device, aligning bus_lower
> to a 1MB boundary first. That leaves it still at 0x1600.
>
>   - Find the EG20T bridge device, which we find has a 64KiB ROM. We
> assign it the address range 0x1600-0x1600 which leaves
> bus_lower at 0x1601.
>
>   - Probe the bus beneath the EG20T bridge device, aligning bus_lower to
> a 1MB boundary first. This leaves bus_lower at 0x1610, which is
> the end of the available memory space.
>
>   - Find the various peripheral devices the EG20T contains, but fail to
> assign any memory space to them since bus_lower is at the end of the
> memory space available to the PCI bus.
>
> Fix this by disabling that 1MB alignment, which allows all of the EG20T
> peripheral devices to be assigned memory space within the 1MB region
> available.
>
> Signed-off-by: Paul Burton 
>
> ---
>
>  configs/boston32r2_defconfig   | 1 +
>  configs/boston32r2el_defconfig | 1 +
>  configs/boston64r2_defconfig   | 1 +
>  configs/boston64r2el_defconfig | 1 +
>  4 files changed, 4 insertions(+)
>

Reviewed-by: Bin Meng 
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Re: [U-Boot] [PATCH 09/23] boston: Disable PCI bridge memory space alignment

[Simon Glass]

On 26 September 2016 at 12:29, Paul Burton  wrote:
> On the MIPS Boston development board we have an Intel EG20T Platform
> Controller Hub connected to a Xilinx AXI to PCIe root port which is only
> assigned a 1MB memory region. The Intel EG20T contains a bridge device
> beneath which all of its peripheral devices can be found, and that
> bridge device contains a ROM. If we align to 1MB when we encounter each
> bridge device we therefore do something like this:
>
>   - Start with bus_lower at 0x1600.
>
>   - Find the Xilinx root bridge, which has no visible BARs so we do very
> little to it.
>
>   - Probe the bus beneath the Xilinx bridge device, aligning bus_lower
> to a 1MB boundary first. That leaves it still at 0x1600.
>
>   - Find the EG20T bridge device, which we find has a 64KiB ROM. We
> assign it the address range 0x1600-0x1600 which leaves
> bus_lower at 0x1601.
>
>   - Probe the bus beneath the EG20T bridge device, aligning bus_lower to
> a 1MB boundary first. This leaves bus_lower at 0x1610, which is
> the end of the available memory space.
>
>   - Find the various peripheral devices the EG20T contains, but fail to
> assign any memory space to them since bus_lower is at the end of the
> memory space available to the PCI bus.
>
> Fix this by disabling that 1MB alignment, which allows all of the EG20T
> peripheral devices to be assigned memory space within the 1MB region
> available.
>
> Signed-off-by: Paul Burton 
>
> ---
>
>  configs/boston32r2_defconfig   | 1 +
>  configs/boston32r2el_defconfig | 1 +
>  configs/boston64r2_defconfig   | 1 +
>  configs/boston64r2el_defconfig | 1 +
>  4 files changed, 4 insertions(+)

Reviewed-by: Simon Glass 
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[U-Boot] [PATCH 09/23] boston: Disable PCI bridge memory space alignment

[Paul Burton]

On the MIPS Boston development board we have an Intel EG20T Platform
Controller Hub connected to a Xilinx AXI to PCIe root port which is only
assigned a 1MB memory region. The Intel EG20T contains a bridge device
beneath which all of its peripheral devices can be found, and that
bridge device contains a ROM. If we align to 1MB when we encounter each
bridge device we therefore do something like this:

  - Start with bus_lower at 0x1600.

  - Find the Xilinx root bridge, which has no visible BARs so we do very
little to it.

  - Probe the bus beneath the Xilinx bridge device, aligning bus_lower
to a 1MB boundary first. That leaves it still at 0x1600.

  - Find the EG20T bridge device, which we find has a 64KiB ROM. We
assign it the address range 0x1600-0x1600 which leaves
bus_lower at 0x1601.

  - Probe the bus beneath the EG20T bridge device, aligning bus_lower to
a 1MB boundary first. This leaves bus_lower at 0x1610, which is
the end of the available memory space.

  - Find the various peripheral devices the EG20T contains, but fail to
assign any memory space to them since bus_lower is at the end of the
memory space available to the PCI bus.

Fix this by disabling that 1MB alignment, which allows all of the EG20T
peripheral devices to be assigned memory space within the 1MB region
available.

Signed-off-by: Paul Burton 

---

 configs/boston32r2_defconfig   | 1 +
 configs/boston32r2el_defconfig | 1 +
 configs/boston64r2_defconfig   | 1 +
 configs/boston64r2el_defconfig | 1 +
 4 files changed, 4 insertions(+)

diff --git a/configs/boston32r2_defconfig b/configs/boston32r2_defconfig
index ca66248..e5f61b8 100644
--- a/configs/boston32r2_defconfig
+++ b/configs/boston32r2_defconfig
@@ -36,6 +36,7 @@ CONFIG_CFI_FLASH=y
 CONFIG_DM_ETH=y
 CONFIG_PCH_GBE=y
 CONFIG_DM_PCI=y
+CONFIG_DM_PCI_BRIDGE_MEM_ALIGN=0x0
 CONFIG_PCI_XILINX=y
 CONFIG_SYS_NS16550=y
 CONFIG_LZ4=y
diff --git a/configs/boston32r2el_defconfig b/configs/boston32r2el_defconfig
index 67f54bf..e9a23b8 100644
--- a/configs/boston32r2el_defconfig
+++ b/configs/boston32r2el_defconfig
@@ -37,6 +37,7 @@ CONFIG_CFI_FLASH=y
 CONFIG_DM_ETH=y
 CONFIG_PCH_GBE=y
 CONFIG_DM_PCI=y
+CONFIG_DM_PCI_BRIDGE_MEM_ALIGN=0x0
 CONFIG_PCI_XILINX=y
 CONFIG_SYS_NS16550=y
 CONFIG_LZ4=y
diff --git a/configs/boston64r2_defconfig b/configs/boston64r2_defconfig
index 1245d1b..55943c5 100644
--- a/configs/boston64r2_defconfig
+++ b/configs/boston64r2_defconfig
@@ -36,6 +36,7 @@ CONFIG_CFI_FLASH=y
 CONFIG_DM_ETH=y
 CONFIG_PCH_GBE=y
 CONFIG_DM_PCI=y
+CONFIG_DM_PCI_BRIDGE_MEM_ALIGN=0x0
 CONFIG_PCI_XILINX=y
 CONFIG_SYS_NS16550=y
 CONFIG_LZ4=y
diff --git a/configs/boston64r2el_defconfig b/configs/boston64r2el_defconfig
index 9b5fa5a..865177d 100644
--- a/configs/boston64r2el_defconfig
+++ b/configs/boston64r2el_defconfig
@@ -37,6 +37,7 @@ CONFIG_CFI_FLASH=y
 CONFIG_DM_ETH=y
 CONFIG_PCH_GBE=y
 CONFIG_DM_PCI=y
+CONFIG_DM_PCI_BRIDGE_MEM_ALIGN=0x0
 CONFIG_PCI_XILINX=y
 CONFIG_SYS_NS16550=y
 CONFIG_LZ4=y
-- 
2.10.0

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