Re: [U-Boot] [PATCH 1/1] arm: socfpga: Add support for the ReflexCES R329 board

2018-07-25 Thread Marek Vasut 
On 07/24/2018 07:21 PM, Xavier Ruppen wrote:
> The ReflexCES PCIe carrier board Arria 10 SoC SoM (R329) provides
> access to all the features of the Arria 10 SoC SoM (R315) (Ethernet,
> OTG USB, Transceivers, UART) and adds further functions, including SFP+
> connectors, PCIe x8 Gen3, USB3.0 and a wifi interface.
> 
> No fpga portion is provided in fit_spl_fpga.its as MSEL is hardwired on
> this board. Thus, a bitstream is loaded before booting by using the EPCQ.
> It is possible to load a bitstream from the HPS (packaged in the .sfp file)
> but a small hardware mod on the MSEL lines is required (tested and works).
> 
> Signed-off-by: Xavier Ruppen 
> Cc: Marek Vasut 
> Cc: Chin Liang See 
> Cc: Dinh Nguyen 
> ---
> 
> This patch was created and tested against u-boot-socfpga/arria10_sdmmc.

Can it be based on u-boot/master and does it work ? I am not accepting
patches on top of these random branches.

> The handoff.dtsi file was created by meld'ing the (old) .dts file provided
> by ReflexCES and socfpga_arria10_socdk_sdmmc_handoff.dtsi.
> 
> The board was tested with what I believe is the factory bitstream written
> in the EPCQ.
> 
> As I copied and pasted the majority of the files from the arria10-socdk,
> I purposely ignored a bunch of checkpatch warnings, i.e. lenghty lines
> and a missing SPDX-License-Identifier in the .dts(i) files.

Those should be fixed ...

[...]

> +++ b/include/configs/socfpga_r329_a10_pcie.h
> @@ -0,0 +1,50 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + *  Copyright (C) 2015-2017 Altera Corporation 
> + */
> +
> +#ifndef __CONFIG_SOCFGPA_ARRIA10_H__
> +#define __CONFIG_SOCFGPA_ARRIA10_H__
> +
> +#include 
> +
> +/* Booting Linux */
> +#define CONFIG_LOADADDR  0x0100
> +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
> +
> +/*
> + * U-Boot general configurations
> + */
> +/* Cache options */
> +#define CONFIG_SYS_DCACHE_OFF

Is this needed ?

> +/* Memory configurations  */
> +#define PHYS_SDRAM_1_SIZE0xC000
> +
> +/* Ethernet on SoC (EMAC) */

The comments need cleanup.

> +/*
> + * U-Boot environment configurations
> + */
> +
> +/*
> + * Serial / UART configurations
> + */
> +#define CONFIG_SYS_NS16550_MEM32

Needed ?

> +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}

Needed ?

If so, should be enabled on all socfpgas .

> +/*
> + * L4 OSC1 Timer 0
> + */
> +/* reload value when timer count to zero */
> +#define TIMER_LOAD_VAL   0x
> +
> +/*
> + * Flash configurations
> + */
> +#define CONFIG_SYS_MAX_FLASH_BANKS 1
> +
> +/* The rest of the configuration is shared */
> +#include 
> +
> +#endif   /* __CONFIG_SOCFGPA_ARRIA10_H__ */
> 


-- 
Best regards,
Marek Vasut
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[U-Boot] [PATCH 1/1] arm: socfpga: Add support for the ReflexCES R329 board

2018-07-24 Thread Xavier Ruppen 
The ReflexCES PCIe carrier board Arria 10 SoC SoM (R329) provides
access to all the features of the Arria 10 SoC SoM (R315) (Ethernet,
OTG USB, Transceivers, UART) and adds further functions, including SFP+
connectors, PCIe x8 Gen3, USB3.0 and a wifi interface.

No fpga portion is provided in fit_spl_fpga.its as MSEL is hardwired on
this board. Thus, a bitstream is loaded before booting by using the EPCQ.
It is possible to load a bitstream from the HPS (packaged in the .sfp file)
but a small hardware mod on the MSEL lines is required (tested and works).

Signed-off-by: Xavier Ruppen 
Cc: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
---

This patch was created and tested against u-boot-socfpga/arria10_sdmmc.

The handoff.dtsi file was created by meld'ing the (old) .dts file provided
by ReflexCES and socfpga_arria10_socdk_sdmmc_handoff.dtsi.

The board was tested with what I believe is the factory bitstream written
in the EPCQ.

As I copied and pasted the majority of the files from the arria10-socdk,
I purposely ignored a bunch of checkpatch warnings, i.e. lenghty lines
and a missing SPDX-License-Identifier in the .dts(i) files.

 arch/arm/dts/Makefile |   1 +
 arch/arm/dts/socfpga_arria10_r329.dts | 108 ++
 .../arm/dts/socfpga_arria10_r329_handoff.dtsi | 350 ++
 arch/arm/mach-socfpga/Kconfig |   7 +
 board/reflexces/r329-a10-pcie/Kconfig |  18 +
 board/reflexces/r329-a10-pcie/MAINTAINERS |   8 +
 board/reflexces/r329-a10-pcie/Makefile|   5 +
 .../reflexces/r329-a10-pcie/fit_spl_fpga.its  |  45 +++
 board/reflexces/r329-a10-pcie/socfpga.c   |   6 +
 configs/socfpga_r329_a10_pcie_defconfig   |  67 
 include/configs/socfpga_r329_a10_pcie.h   |  50 +++
 11 files changed, 665 insertions(+)
 create mode 100644 arch/arm/dts/socfpga_arria10_r329.dts
 create mode 100644 arch/arm/dts/socfpga_arria10_r329_handoff.dtsi
 create mode 100644 board/reflexces/r329-a10-pcie/Kconfig
 create mode 100644 board/reflexces/r329-a10-pcie/MAINTAINERS
 create mode 100644 board/reflexces/r329-a10-pcie/Makefile
 create mode 100644 board/reflexces/r329-a10-pcie/fit_spl_fpga.its
 create mode 100644 board/reflexces/r329-a10-pcie/socfpga.c
 create mode 100644 configs/socfpga_r329_a10_pcie_defconfig
 create mode 100644 include/configs/socfpga_r329_a10_pcie.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 946023093d..05cd7af467 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -188,6 +188,7 @@ dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
 dtb-$(CONFIG_ARCH_SOCFPGA) +=  \
socfpga_arria5_socdk.dtb\
socfpga_arria10_socdk_sdmmc.dtb \
+   socfpga_arria10_r329.dtb\
socfpga_cyclone5_is1.dtb\
socfpga_cyclone5_socdk.dtb  \
socfpga_cyclone5_dbm_soc1.dtb   \
diff --git a/arch/arm/dts/socfpga_arria10_r329.dts 
b/arch/arm/dts/socfpga_arria10_r329.dts
new file mode 100644
index 00..8869ef0fe7
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_r329.dts
@@ -0,0 +1,108 @@
+/*
+ * Copyright (C) 2015 Altera Corporation 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+
+/dts-v1/;
+#include "socfpga_arria10_r329_handoff.dtsi"
+
+/ {
+   model = "Reflex CES R329 SOM-A10 PCIe";
+   compatible = "altr,socfpga-arria10", "altr,socfpga";
+
+   aliases {
+   ethernet0 = 
+   serial0 = 
+   };
+
+   chosen {
+   bootargs = "earlyprintk";
+   stdout-path = "serial0:115200n8";
+   };
+
+   memory@0 {
+   name = "memory";
+   device_type = "memory";
+   reg = <0x0 0xC000>; /* 3GB */
+   };
+
+   soc {
+   u-boot,dm-pre-reloc;
+   };
+};
+
+ {
+   phy-mode = "rgmii";
+   phy-addr = <0x>; /* probe for phy addr */
+
+   /*
+* These skews assume the user's FPGA design is adding 600ps of delay
+* for TX_CLK on Arria 10.
+*
+* All skews are offset since hardware skew values for the ksz9031
+* range from a negative skew to a positive skew.
+* See the micrel-ksz90x1.txt Documentation file for details.
+*/
+   txd0-skew-ps