subject:"\[U\-Boot\] \[PATCH 1\/2\]\[v2\] PBL\: add support for boot from SPI flash."

Re: [U-Boot] [PATCH 1/2][v2] PBL: add support for boot from SPI flash.

2010-12-15 Thread Kumar Gala


On Nov 16, 2010, at 2:48 AM, Shaohui Xie wrote:

> PBL: SPI flash used as RCW and PBI source, CPC used as 1M SRAM
> where PBL will copy whole U-BOOT image to, U-boot can boot from CPC
> after PBL completes RCW and PBI phases.
> 
> Signed-off-by: Chunhe Lan 
> Signed-off-by: Mingkai Hu 
> Signed-off-by: Shaohui Xie 
> ---
> arch/powerpc/cpu/mpc85xx/cpu_init.c  |   17 +
> board/freescale/corenet_ds/config.mk |6 ++
> board/freescale/corenet_ds/tlb.c |9 +
> boards.cfg   |1 +
> include/configs/corenet_ds.h |   31 +--
> 5 files changed, 62 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c 
> b/arch/powerpc/cpu/mpc85xx/cpu_init.c
> index 27236a0..cff7ac3 100644
> --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
> +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
> @@ -139,6 +139,20 @@ static void enable_cpc(void)
>   for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
>   u32 cpccfg0 = in_be32(&cpc->cpccfg0);
>   size += CPC_CFG0_SZ_K(cpccfg0);
> + if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
> + /* find and disable LAW of SRAM */
> + struct law_entry law = 
> find_law(CONFIG_SYS_INIT_L3_ADDR);
> +
> + if (law.index == -1) {
> + printf("\nFatal error happened\n");
> + return;
> + } else
> + disable_law(law.index);
> +
> + clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
> + out_be32(&cpc->cpccsr0, 0);
> + out_be32(&cpc->cpcsrcr0, 0);
> + }
> 
>   out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
>   /* Read back to sync write */
> @@ -155,6 +169,9 @@ void invalidate_cpc(void)
>   cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
> 
>   for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
> + /* skip CPC when it used as all SRAM */
> + if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
> + continue;
>   /* Flash invalidate the CPC and clear all the locks */
>   out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
>   while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
> diff --git a/board/freescale/corenet_ds/config.mk 
> b/board/freescale/corenet_ds/config.mk
> index 15bbf20..31b3379 100644
> --- a/board/freescale/corenet_ds/config.mk
> +++ b/board/freescale/corenet_ds/config.mk
> @@ -24,4 +24,10 @@
> # P4080DS board
> #
> 
> +ifeq ($(CONFIG_PBL_BOOT_INDIRECT), y)
> +RESET_VECTOR_ADDRESS = 0xfffc
> +endif
> +
> +ifndef RESET_VECTOR_ADDRESS
> RESET_VECTOR_ADDRESS = 0xeffc
> +endif
> diff --git a/board/freescale/corenet_ds/tlb.c 
> b/board/freescale/corenet_ds/tlb.c
> index 1ae0416..08f91a7 100644
> --- a/board/freescale/corenet_ds/tlb.c
> +++ b/board/freescale/corenet_ds/tlb.c
> @@ -51,9 +51,18 @@ struct fsl_e_tlb_entry tlb_table[] = {
> 
>   /* TLB 1 */
>   /* *I*** - Covers boot page */
> +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
> + /* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
> +  * SRAM is at 0xfff0, it covered the 0xf000.
> +  * */
> + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
> + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> + 0, 0, BOOKE_PAGESZ_1M, 1),
> +#else
>   SET_TLB_ENTRY(1, 0xf000, 0xf000,
> MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> 0, 0, BOOKE_PAGESZ_4K, 1),
> +#endif
> 
>   /* *I*G* - CCSRBAR */
>   SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
> diff --git a/boards.cfg b/boards.cfg
> index 6c2a667..168d6f5 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -195,6 +195,7 @@ P1022DS   powerpc mpc85xx p1022ds 
> freescale
> P2020DS   powerpc mpc85xx p2020ds freescale
> stxgp3powerpc mpc85xx stxgp3  stx
> P4080DS   powerpc mpc85xx corenet_ds  freescale
> +P4080DS_PBL_BOOT_INDIRECTpowerpc mpc85xx corenet_ds  
> freescale   -   P4080DS:PBL_BOOT_INDIRECT,SYS_TEXT_BASE=0xFFF8
> sbc8540   powerpc mpc85xx sbc8560 -   
> -   SBC8540
> sbc8548   powerpc mpc85xx sbc8548 -   
> -   sbc8548
> sbc8560   powerpc mpc85xx sbc8560 -   
> -   sbc8560
> diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
> index 2ac59e5..0776c3b 100644
> --- a/include/configs/corenet_ds.h
> +++ b/include/configs/corenet_ds.h
> @@ -28,6 +28,11 @@
> 
> #include "../board/freescale/common/ics307_clk.h"
>

Re: [U-Boot] [PATCH 1/2][v2] PBL: add support for boot from SPI flash.

2010-11-16 Thread Wolfgang Denk

Dear Shaohui Xie,

In message <1289897285-16845-1-git-send-email-b21...@freescale.com> you wrote:
> PBL: SPI flash used as RCW and PBI source, CPC used as 1M SRAM
> where PBL will copy whole U-BOOT image to, U-boot can boot from CPC
> after PBL completes RCW and PBI phases.

Can you please write plain text?  What does all these TLAs mean?

PBL ?
PBI ?
CPC ?


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
Remember thee Ay, thou poor ghost while memory holds a seat  In  this
distracted  globe.  Remember  thee!  Yea, from the table of my memory
I'll wipe away all trivial fond  records,  All  saws  of  books,  all
forms,  all  pressures past, That youth and observation copied there.
Hamlet, I : v : 95 William Shakespeare
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 1/2][v2] PBL: add support for boot from SPI flash.

2010-11-16 Thread Shaohui Xie

PBL: SPI flash used as RCW and PBI source, CPC used as 1M SRAM
where PBL will copy whole U-BOOT image to, U-boot can boot from CPC
after PBL completes RCW and PBI phases.

Signed-off-by: Chunhe Lan 
Signed-off-by: Mingkai Hu 
Signed-off-by: Shaohui Xie 
---
 arch/powerpc/cpu/mpc85xx/cpu_init.c  |   17 +
 board/freescale/corenet_ds/config.mk |6 ++
 board/freescale/corenet_ds/tlb.c |9 +
 boards.cfg   |1 +
 include/configs/corenet_ds.h |   31 +--
 5 files changed, 62 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c 
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 27236a0..cff7ac3 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -139,6 +139,20 @@ static void enable_cpc(void)
for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
u32 cpccfg0 = in_be32(&cpc->cpccfg0);
size += CPC_CFG0_SZ_K(cpccfg0);
+   if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
+   /* find and disable LAW of SRAM */
+   struct law_entry law = 
find_law(CONFIG_SYS_INIT_L3_ADDR);
+
+   if (law.index == -1) {
+   printf("\nFatal error happened\n");
+   return;
+   } else
+   disable_law(law.index);
+
+   clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
+   out_be32(&cpc->cpccsr0, 0);
+   out_be32(&cpc->cpcsrcr0, 0);
+   }
 
out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
/* Read back to sync write */
@@ -155,6 +169,9 @@ void invalidate_cpc(void)
cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
 
for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
+   /* skip CPC when it used as all SRAM */
+   if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
+   continue;
/* Flash invalidate the CPC and clear all the locks */
out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
diff --git a/board/freescale/corenet_ds/config.mk 
b/board/freescale/corenet_ds/config.mk
index 15bbf20..31b3379 100644
--- a/board/freescale/corenet_ds/config.mk
+++ b/board/freescale/corenet_ds/config.mk
@@ -24,4 +24,10 @@
 # P4080DS board
 #
 
+ifeq ($(CONFIG_PBL_BOOT_INDIRECT), y)
+RESET_VECTOR_ADDRESS = 0xfffc
+endif
+
+ifndef RESET_VECTOR_ADDRESS
 RESET_VECTOR_ADDRESS = 0xeffc
+endif
diff --git a/board/freescale/corenet_ds/tlb.c b/board/freescale/corenet_ds/tlb.c
index 1ae0416..08f91a7 100644
--- a/board/freescale/corenet_ds/tlb.c
+++ b/board/freescale/corenet_ds/tlb.c
@@ -51,9 +51,18 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
/* TLB 1 */
/* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+   /* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
+* SRAM is at 0xfff0, it covered the 0xf000.
+* */
+   SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+   MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+   0, 0, BOOKE_PAGESZ_1M, 1),
+#else
SET_TLB_ENTRY(1, 0xf000, 0xf000,
  MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
 
/* *I*G* - CCSRBAR */
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
diff --git a/boards.cfg b/boards.cfg
index 6c2a667..168d6f5 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -195,6 +195,7 @@ P1022DS powerpc mpc85xx p1022ds 
freescale
 P2020DSpowerpc mpc85xx p2020ds freescale
 stxgp3 powerpc mpc85xx stxgp3  stx
 P4080DSpowerpc mpc85xx corenet_ds  freescale
+P4080DS_PBL_BOOT_INDIRECT  powerpc mpc85xx corenet_ds  
freescale   -   P4080DS:PBL_BOOT_INDIRECT,SYS_TEXT_BASE=0xFFF8
 sbc8540powerpc mpc85xx sbc8560 -   
-   SBC8540
 sbc8548powerpc mpc85xx sbc8548 -   
-   sbc8548
 sbc8560powerpc mpc85xx sbc8560 -   
-   sbc8560
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 2ac59e5..0776c3b 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -28,6 +28,11 @@
 
 #include "../board/freescale/common/ics307_clk.h"
 
+#ifdef CONFIG_PBL_BOOT_INDIRECT
+#define CONFIG_RAMBOOT_PBL 1
+#define CONFIG_RAMBOOT_TEXT_BASE0xfff8
+#endif
+
 /* High Level Configuration Options */
 #def

Re: [U-Boot] [PATCH 1/2][v2] PBL: add support for boot from SPI flash.

Re: [U-Boot] [PATCH 1/2][v2] PBL: add support for boot from SPI flash.

[U-Boot] [PATCH 1/2][v2] PBL: add support for boot from SPI flash.

3 matches

Site Navigation

Mail list logo

Footer information