[U-Boot] [PATCH 1/2] ARM: tegra: Make cache line size SoC specific
From: Thierry Reding Currently all Tegra SoCs are assumed to have 32 byte cache lines. This isn't true for Tegra114, however, which uses 4 Cortex-A15 cores and therefore uses a cache line size of 64 bytes. Move the cache line size setting to the per-SoC common configuration file. Signed-off-by: Thierry Reding --- include/configs/tegra-common.h| 2 -- include/configs/tegra114-common.h | 3 +++ include/configs/tegra20-common.h | 3 +++ include/configs/tegra30-common.h | 3 +++ 4 files changed, 9 insertions(+), 2 deletions(-) diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index cb9e7c3..056207b 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -33,8 +33,6 @@ #define CONFIG_TEGRA /* which is a Tegra generic machine */ #define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */ -#define CONFIG_SYS_CACHELINE_SIZE 32 - #include /* get chip and board defs */ /* diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h index 44e98e5..c3de9a9 100644 --- a/include/configs/tegra114-common.h +++ b/include/configs/tegra114-common.h @@ -18,6 +18,9 @@ #define _TEGRA114_COMMON_H_ #include "tegra-common.h" +/* Cortex-A15 uses a cache line size of 64 bytes */ +#define CONFIG_SYS_CACHELINE_SIZE 64 + /* * NS16550 Configuration */ diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index d5abecb..b334b33 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -25,6 +25,9 @@ #define _TEGRA20_COMMON_H_ #include "tegra-common.h" +/* Cortex-A9 uses a cache line size of 32 bytes */ +#define CONFIG_SYS_CACHELINE_SIZE 32 + /* * Errata configuration */ diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h index 7ea36be..a72dc13 100644 --- a/include/configs/tegra30-common.h +++ b/include/configs/tegra30-common.h @@ -25,6 +25,9 @@ #define _TEGRA30_COMMON_H_ #include "tegra-common.h" +/* Cortex-A9 uses a cache line size of 32 bytes */ +#define CONFIG_SYS_CACHELINE_SIZE 32 + /* * Errata configuration */ -- 1.8.1.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] ARM: tegra: Make cache line size SoC specific
On 07/18/2013 01:13 PM, Thierry Reding wrote: > From: Thierry Reding > > Currently all Tegra SoCs are assumed to have 32 byte cache lines. This > isn't true for Tegra114, however, which uses 4 Cortex-A15 cores and > therefore uses a cache line size of 64 bytes. Move the cache line size > setting to the per-SoC common configuration file. Tested-by: Stephen Warren Reviewed-by: Stephen Warren ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] ARM: tegra: Make cache line size SoC specific
On Thu, Jul 18, 2013 at 03:19:18PM -0600, Stephen Warren wrote: > On 07/18/2013 01:13 PM, Thierry Reding wrote: > > From: Thierry Reding > > > > Currently all Tegra SoCs are assumed to have 32 byte cache lines. This > > isn't true for Tegra114, however, which uses 4 Cortex-A15 cores and > > therefore uses a cache line size of 64 bytes. Move the cache line size > > setting to the per-SoC common configuration file. > > Tested-by: Stephen Warren > Reviewed-by: Stephen Warren Do these apply to patch 2 of this series as well? Thierry pgp2FlszQ_lEZ.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] ARM: tegra: Make cache line size SoC specific
On 07/18/2013 08:38 PM, Thierry Reding wrote: > On Thu, Jul 18, 2013 at 03:19:18PM -0600, Stephen Warren wrote: >> On 07/18/2013 01:13 PM, Thierry Reding wrote: >>> From: Thierry Reding >>> >>> Currently all Tegra SoCs are assumed to have 32 byte cache >>> lines. This isn't true for Tegra114, however, which uses 4 >>> Cortex-A15 cores and therefore uses a cache line size of 64 >>> bytes. Move the cache line size setting to the per-SoC common >>> configuration file. >> >> Tested-by: Stephen Warren Reviewed-by: >> Stephen Warren > > Do these apply to patch 2 of this series as well? Yes, the whole series. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] ARM: tegra: Make cache line size SoC specific
On 07/18/2013 01:13 PM, Thierry Reding wrote: > From: Thierry Reding > > Currently all Tegra SoCs are assumed to have 32 byte cache lines. This > isn't true for Tegra114, however, which uses 4 Cortex-A15 cores and > therefore uses a cache line size of 64 bytes. Move the cache line size > setting to the per-SoC common configuration file. Tom, can these two patches be applied please? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] ARM: tegra: Make cache line size SoC specific
Sure, your mkimage patch, and Thierry's 2 cache patches have been applied to u-boot-tegra/next (after rebasing next against Albert's ARM master), build tested (all Tegra boards build fine), and pushed to denx. Also updated u-boot-tegra/master w/Albert's ARM TOT. Sorry for the delay, really busy w/new stuff. Ping me if I get behind again. Thanks, Tom > -Original Message- > From: Stephen Warren [mailto:swar...@wwwdotorg.org] > Sent: Wednesday, August 14, 2013 9:05 AM > To: Tom Warren > Cc: Thierry Reding; u-boot@lists.denx.de; Thierry Reding; Stephen Warren > Subject: Re: [U-Boot] [PATCH 1/2] ARM: tegra: Make cache line size SoC > specific > > On 07/18/2013 01:13 PM, Thierry Reding wrote: > > From: Thierry Reding > > > > Currently all Tegra SoCs are assumed to have 32 byte cache lines. This > > isn't true for Tegra114, however, which uses 4 Cortex-A15 cores and > > therefore uses a cache line size of 64 bytes. Move the cache line size > > setting to the per-SoC common configuration file. > > Tom, can these two patches be applied please? --- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. --- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
