SGMII5/6 and SGMII7/8 are not on the same slot on P5040
according to the serdes protocol.
So it is not proper to organize SGMII5/6 and SGMII7/8
on one bus and SGMII5/6 can't work.
So a new bus SUPER_HYDRA_FM3_SGMII_MDIO is added for
SGMII5/6
Signed-off-by: Zhao Qiang b45...@freescale.com
---
board/freescale/corenet_ds/eth_superhydra.c | 22 ++
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/board/freescale/corenet_ds/eth_superhydra.c
b/board/freescale/corenet_ds/eth_superhydra.c
index ae07073..00925a6 100644
--- a/board/freescale/corenet_ds/eth_superhydra.c
+++ b/board/freescale/corenet_ds/eth_superhydra.c
@@ -465,6 +465,8 @@ int board_eth_init(bd_t *bis)
SUPER_HYDRA_FM1_SGMII_MDIO);
super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
SUPER_HYDRA_FM2_SGMII_MDIO);
+ super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
+ SUPER_HYDRA_FM3_SGMII_MDIO);
super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME,
SUPER_HYDRA_FM1_TGEC_MDIO);
super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME,
@@ -654,10 +656,22 @@ int board_eth_init(bd_t *bis)
break;
};
- super_hydra_mdio_set_mux(SUPER_HYDRA_FM2_SGMII_MDIO,
- mdio_mux[i].mask, mdio_mux[i].val);
- fm_info_set_mdio(i,
- miiphy_get_dev_by_name(SUPER_HYDRA_FM2_SGMII_MDIO));
+ if (i == FM2_DTSEC1 || i == FM2_DTSEC2) {
+ super_hydra_mdio_set_mux(
+ SUPER_HYDRA_FM3_SGMII_MDIO,
+ mdio_mux[i].mask,
+ mdio_mux[i].val);
+ fm_info_set_mdio(i, miiphy_get_dev_by_name(
+ SUPER_HYDRA_FM3_SGMII_MDIO));
+ } else {
+ super_hydra_mdio_set_mux(
+ SUPER_HYDRA_FM2_SGMII_MDIO,
+ mdio_mux[i].mask,
+ mdio_mux[i].val);
+ fm_info_set_mdio(i, miiphy_get_dev_by_name(
+ SUPER_HYDRA_FM2_SGMII_MDIO));
+ }
+
break;
case PHY_INTERFACE_MODE_RGMII:
/*
--
1.8.0
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