Re: [U-Boot] [PATCH 1/2] MSCC: Add sysreset drivers for MSCC Socs
Hi Daniel,
The 01/16/2019 15:22, Daniel Schwierzeck wrote:
>
>
> Am 15.01.19 um 17:33 schrieb Horatiu Vultur:
> > Add sysreset driver for Luton, Ocelot and Jaguar2 SoCs.
> >
> > Signed-off-by: Horatiu Vultur
> > ---
> > MAINTAINERS | 1 +
> > arch/mips/dts/mscc,jr2.dtsi | 7 +-
> > arch/mips/dts/mscc,luton.dtsi| 10 +++
> > arch/mips/dts/mscc,ocelot.dtsi | 5 ++
> > board/mscc/ocelot/ocelot.c | 20 +
> > configs/mscc_jr2_defconfig | 2 +
> > configs/mscc_luton_defconfig | 2 +
> > configs/mscc_ocelot_defconfig| 2 +
> > drivers/sysreset/Kconfig | 6 ++
> > drivers/sysreset/Makefile| 1 +
> > drivers/sysreset/sysreset_mscc.c | 157
> > +++
> > 11 files changed, 212 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/sysreset/sysreset_mscc.c
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 3fa5d3e..fb1b69b 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -527,6 +527,7 @@ F: board/mscc/
> > F: configs/mscc*
> > F: drivers/gpio/mscc_sgpio.c
> > F: drivers/spi/mscc_bb_spi.c
> > +F: drivers/sysreset/sysreset_mscc.c
> > F: include/configs/vcoreiii.h
> > F: drivers/pinctrl/mscc/
> >
> > diff --git a/arch/mips/dts/mscc,jr2.dtsi b/arch/mips/dts/mscc,jr2.dtsi
> > index 0900926..86d1378 100644
> > --- a/arch/mips/dts/mscc,jr2.dtsi
> > +++ b/arch/mips/dts/mscc,jr2.dtsi
> > @@ -52,7 +52,12 @@
> > interrupt-parent = <>;
> >
> > cpu_ctrl: syscon@0 {
> > - compatible = "mscc,jr2-cpu-syscon", "syscon";
> > + compatible = "mscc,jaguar2-cpu-syscon", "syscon";
> > + reg = <0x0 0x2c>;
> > + };
> > +
> > + sysreset: sysreset@0 {
> > + compatible = "mscc,jaguar2-chip-reset";
> > reg = <0x0 0x2c>;
> > };
> >
> > diff --git a/arch/mips/dts/mscc,luton.dtsi b/arch/mips/dts/mscc,luton.dtsi
> > index d11ec48..7cbb53b 100644
> > --- a/arch/mips/dts/mscc,luton.dtsi
> > +++ b/arch/mips/dts/mscc,luton.dtsi
> > @@ -42,6 +42,16 @@
> > #size-cells = <1>;
> > ranges = <0 0x6000 0x1020>;
> >
> > + cpu_ctrl: syscon@0 {
> > + compatible = "mscc,luton-cpu-syscon", "syscon";
> > + reg = <0x0 0x2c>;
> > + };
> > +
> > + sysreset: sysreset@70090 {
> > + compatible = "mscc,luton-chip-reset";
> > + reg = <0x70090 0x2c>;
> > + };
> > +
> > uart0: serial@1010 {
> > pinctrl-0 = <_pins>;
> > pinctrl-names = "default";
> > diff --git a/arch/mips/dts/mscc,ocelot.dtsi b/arch/mips/dts/mscc,ocelot.dtsi
> > index 2592003..4287117 100644
> > --- a/arch/mips/dts/mscc,ocelot.dtsi
> > +++ b/arch/mips/dts/mscc,ocelot.dtsi
> > @@ -62,6 +62,11 @@
> > reg = <0x0 0x2c>;
> > };
> >
> > + sysreset: sysreset@1070008 {
> > + compatible = "mscc,ocelot-chip-reset";
> > + reg = <0x1070008 0x4>;
> > + };
> > +
> > intc: interrupt-controller@70 {
> > compatible = "mscc,ocelot-icpu-intr";
> > reg = <0x70 0x70>;
> > diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c
> > index 0f7a532..ae5eb4d 100644
> > --- a/board/mscc/ocelot/ocelot.c
> > +++ b/board/mscc/ocelot/ocelot.c
> > @@ -10,6 +10,7 @@
> > #include
> > #include
> > #include
> > +#include
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > @@ -25,6 +26,25 @@ void board_debug_uart_init(void)
> > mscc_gpio_set_alternate(7, 1);
> > }
> >
> > +__weak int ocelot_sysreset_request(struct udevice *dev,
> > + enum sysreset_t type)
> > +{
> > + u32 resetbits = PERF_SOFT_RST_SOFT_CHIP_RST;
> > + (void)readl(BASE_DEVCPU_GCB + PERF_SOFT_RST);
> > +
> > + /* Make sure VCore is NOT protected from reset */
> > + clrbits_le32(BASE_CFG + ICPU_RESET, ICPU_RESET_CORE_RST_PROTECT);
> > +
> > + /* Change to SPI bitbang for SPI reset workaround... */
> > + writel(ICPU_SW_MODE_SW_SPI_CS_OE(1) | ICPU_SW_MODE_SW_SPI_CS(1) |
> > + ICPU_SW_MODE_SW_PIN_CTRL_MODE, BASE_CFG + ICPU_SW_MODE);
> > +
> > + /* Do the global reset */
> > + writel(resetbits, BASE_DEVCPU_GCB + PERF_SOFT_RST);
> > +
> > + return -EINPROGRESS;
> > +}
>
> is this a difference between Luton and Ocelot or only for one board
> based on Ocelot platform? I'm asking because you register the same
> sysreset_request for Luton and Ocelot but for Ocelot you override it
> again with an Ocelot board-specific function. This looks a little bit
> strange ;)
>
There is no difference between the Luton and Ocelot regarding reset, but
there is an issue on boards based on Ocelot platform. So that's the
reason I marked the function as weak and overwrite it in
Re: [U-Boot] [PATCH 1/2] MSCC: Add sysreset drivers for MSCC Socs
Am 15.01.19 um 17:33 schrieb Horatiu Vultur:
> Add sysreset driver for Luton, Ocelot and Jaguar2 SoCs.
>
> Signed-off-by: Horatiu Vultur
> ---
> MAINTAINERS | 1 +
> arch/mips/dts/mscc,jr2.dtsi | 7 +-
> arch/mips/dts/mscc,luton.dtsi| 10 +++
> arch/mips/dts/mscc,ocelot.dtsi | 5 ++
> board/mscc/ocelot/ocelot.c | 20 +
> configs/mscc_jr2_defconfig | 2 +
> configs/mscc_luton_defconfig | 2 +
> configs/mscc_ocelot_defconfig| 2 +
> drivers/sysreset/Kconfig | 6 ++
> drivers/sysreset/Makefile| 1 +
> drivers/sysreset/sysreset_mscc.c | 157
> +++
> 11 files changed, 212 insertions(+), 1 deletion(-)
> create mode 100644 drivers/sysreset/sysreset_mscc.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 3fa5d3e..fb1b69b 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -527,6 +527,7 @@ F:board/mscc/
> F: configs/mscc*
> F: drivers/gpio/mscc_sgpio.c
> F: drivers/spi/mscc_bb_spi.c
> +F: drivers/sysreset/sysreset_mscc.c
> F: include/configs/vcoreiii.h
> F: drivers/pinctrl/mscc/
>
> diff --git a/arch/mips/dts/mscc,jr2.dtsi b/arch/mips/dts/mscc,jr2.dtsi
> index 0900926..86d1378 100644
> --- a/arch/mips/dts/mscc,jr2.dtsi
> +++ b/arch/mips/dts/mscc,jr2.dtsi
> @@ -52,7 +52,12 @@
> interrupt-parent = <>;
>
> cpu_ctrl: syscon@0 {
> - compatible = "mscc,jr2-cpu-syscon", "syscon";
> + compatible = "mscc,jaguar2-cpu-syscon", "syscon";
> + reg = <0x0 0x2c>;
> + };
> +
> + sysreset: sysreset@0 {
> + compatible = "mscc,jaguar2-chip-reset";
> reg = <0x0 0x2c>;
> };
>
> diff --git a/arch/mips/dts/mscc,luton.dtsi b/arch/mips/dts/mscc,luton.dtsi
> index d11ec48..7cbb53b 100644
> --- a/arch/mips/dts/mscc,luton.dtsi
> +++ b/arch/mips/dts/mscc,luton.dtsi
> @@ -42,6 +42,16 @@
> #size-cells = <1>;
> ranges = <0 0x6000 0x1020>;
>
> + cpu_ctrl: syscon@0 {
> + compatible = "mscc,luton-cpu-syscon", "syscon";
> + reg = <0x0 0x2c>;
> + };
> +
> + sysreset: sysreset@70090 {
> + compatible = "mscc,luton-chip-reset";
> + reg = <0x70090 0x2c>;
> + };
> +
> uart0: serial@1010 {
> pinctrl-0 = <_pins>;
> pinctrl-names = "default";
> diff --git a/arch/mips/dts/mscc,ocelot.dtsi b/arch/mips/dts/mscc,ocelot.dtsi
> index 2592003..4287117 100644
> --- a/arch/mips/dts/mscc,ocelot.dtsi
> +++ b/arch/mips/dts/mscc,ocelot.dtsi
> @@ -62,6 +62,11 @@
> reg = <0x0 0x2c>;
> };
>
> + sysreset: sysreset@1070008 {
> + compatible = "mscc,ocelot-chip-reset";
> + reg = <0x1070008 0x4>;
> + };
> +
> intc: interrupt-controller@70 {
> compatible = "mscc,ocelot-icpu-intr";
> reg = <0x70 0x70>;
> diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c
> index 0f7a532..ae5eb4d 100644
> --- a/board/mscc/ocelot/ocelot.c
> +++ b/board/mscc/ocelot/ocelot.c
> @@ -10,6 +10,7 @@
> #include
> #include
> #include
> +#include
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -25,6 +26,25 @@ void board_debug_uart_init(void)
> mscc_gpio_set_alternate(7, 1);
> }
>
> +__weak int ocelot_sysreset_request(struct udevice *dev,
> +enum sysreset_t type)
> +{
> + u32 resetbits = PERF_SOFT_RST_SOFT_CHIP_RST;
> + (void)readl(BASE_DEVCPU_GCB + PERF_SOFT_RST);
> +
> + /* Make sure VCore is NOT protected from reset */
> + clrbits_le32(BASE_CFG + ICPU_RESET, ICPU_RESET_CORE_RST_PROTECT);
> +
> + /* Change to SPI bitbang for SPI reset workaround... */
> + writel(ICPU_SW_MODE_SW_SPI_CS_OE(1) | ICPU_SW_MODE_SW_SPI_CS(1) |
> +ICPU_SW_MODE_SW_PIN_CTRL_MODE, BASE_CFG + ICPU_SW_MODE);
> +
> + /* Do the global reset */
> + writel(resetbits, BASE_DEVCPU_GCB + PERF_SOFT_RST);
> +
> + return -EINPROGRESS;
> +}
is this a difference between Luton and Ocelot or only for one board
based on Ocelot platform? I'm asking because you register the same
sysreset_request for Luton and Ocelot but for Ocelot you override it
again with an Ocelot board-specific function. This looks a little bit
strange ;)
> +
> int board_early_init_r(void)
> {
> /* Prepare SPI controller to be used in master mode */
> diff --git a/configs/mscc_jr2_defconfig b/configs/mscc_jr2_defconfig
> index b215754..0992185 100644
> --- a/configs/mscc_jr2_defconfig
> +++ b/configs/mscc_jr2_defconfig
> @@ -57,3 +57,5 @@ CONFIG_SPI=y
> CONFIG_DM_SPI=y
> CONFIG_LZMA=y
> CONFIG_XZ=y
> +CONFIG_SYSRESET=y
> +CONFIG_SYSRESET_MSCC=y
> diff --git
[U-Boot] [PATCH 1/2] MSCC: Add sysreset drivers for MSCC Socs
Add sysreset driver for Luton, Ocelot and Jaguar2 SoCs.
Signed-off-by: Horatiu Vultur
---
MAINTAINERS | 1 +
arch/mips/dts/mscc,jr2.dtsi | 7 +-
arch/mips/dts/mscc,luton.dtsi| 10 +++
arch/mips/dts/mscc,ocelot.dtsi | 5 ++
board/mscc/ocelot/ocelot.c | 20 +
configs/mscc_jr2_defconfig | 2 +
configs/mscc_luton_defconfig | 2 +
configs/mscc_ocelot_defconfig| 2 +
drivers/sysreset/Kconfig | 6 ++
drivers/sysreset/Makefile| 1 +
drivers/sysreset/sysreset_mscc.c | 157 +++
11 files changed, 212 insertions(+), 1 deletion(-)
create mode 100644 drivers/sysreset/sysreset_mscc.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 3fa5d3e..fb1b69b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -527,6 +527,7 @@ F: board/mscc/
F: configs/mscc*
F: drivers/gpio/mscc_sgpio.c
F: drivers/spi/mscc_bb_spi.c
+F: drivers/sysreset/sysreset_mscc.c
F: include/configs/vcoreiii.h
F: drivers/pinctrl/mscc/
diff --git a/arch/mips/dts/mscc,jr2.dtsi b/arch/mips/dts/mscc,jr2.dtsi
index 0900926..86d1378 100644
--- a/arch/mips/dts/mscc,jr2.dtsi
+++ b/arch/mips/dts/mscc,jr2.dtsi
@@ -52,7 +52,12 @@
interrupt-parent = <>;
cpu_ctrl: syscon@0 {
- compatible = "mscc,jr2-cpu-syscon", "syscon";
+ compatible = "mscc,jaguar2-cpu-syscon", "syscon";
+ reg = <0x0 0x2c>;
+ };
+
+ sysreset: sysreset@0 {
+ compatible = "mscc,jaguar2-chip-reset";
reg = <0x0 0x2c>;
};
diff --git a/arch/mips/dts/mscc,luton.dtsi b/arch/mips/dts/mscc,luton.dtsi
index d11ec48..7cbb53b 100644
--- a/arch/mips/dts/mscc,luton.dtsi
+++ b/arch/mips/dts/mscc,luton.dtsi
@@ -42,6 +42,16 @@
#size-cells = <1>;
ranges = <0 0x6000 0x1020>;
+ cpu_ctrl: syscon@0 {
+ compatible = "mscc,luton-cpu-syscon", "syscon";
+ reg = <0x0 0x2c>;
+ };
+
+ sysreset: sysreset@70090 {
+ compatible = "mscc,luton-chip-reset";
+ reg = <0x70090 0x2c>;
+ };
+
uart0: serial@1010 {
pinctrl-0 = <_pins>;
pinctrl-names = "default";
diff --git a/arch/mips/dts/mscc,ocelot.dtsi b/arch/mips/dts/mscc,ocelot.dtsi
index 2592003..4287117 100644
--- a/arch/mips/dts/mscc,ocelot.dtsi
+++ b/arch/mips/dts/mscc,ocelot.dtsi
@@ -62,6 +62,11 @@
reg = <0x0 0x2c>;
};
+ sysreset: sysreset@1070008 {
+ compatible = "mscc,ocelot-chip-reset";
+ reg = <0x1070008 0x4>;
+ };
+
intc: interrupt-controller@70 {
compatible = "mscc,ocelot-icpu-intr";
reg = <0x70 0x70>;
diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c
index 0f7a532..ae5eb4d 100644
--- a/board/mscc/ocelot/ocelot.c
+++ b/board/mscc/ocelot/ocelot.c
@@ -10,6 +10,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -25,6 +26,25 @@ void board_debug_uart_init(void)
mscc_gpio_set_alternate(7, 1);
}
+__weak int ocelot_sysreset_request(struct udevice *dev,
+ enum sysreset_t type)
+{
+ u32 resetbits = PERF_SOFT_RST_SOFT_CHIP_RST;
+ (void)readl(BASE_DEVCPU_GCB + PERF_SOFT_RST);
+
+ /* Make sure VCore is NOT protected from reset */
+ clrbits_le32(BASE_CFG + ICPU_RESET, ICPU_RESET_CORE_RST_PROTECT);
+
+ /* Change to SPI bitbang for SPI reset workaround... */
+ writel(ICPU_SW_MODE_SW_SPI_CS_OE(1) | ICPU_SW_MODE_SW_SPI_CS(1) |
+ ICPU_SW_MODE_SW_PIN_CTRL_MODE, BASE_CFG + ICPU_SW_MODE);
+
+ /* Do the global reset */
+ writel(resetbits, BASE_DEVCPU_GCB + PERF_SOFT_RST);
+
+ return -EINPROGRESS;
+}
+
int board_early_init_r(void)
{
/* Prepare SPI controller to be used in master mode */
diff --git a/configs/mscc_jr2_defconfig b/configs/mscc_jr2_defconfig
index b215754..0992185 100644
--- a/configs/mscc_jr2_defconfig
+++ b/configs/mscc_jr2_defconfig
@@ -57,3 +57,5 @@ CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_LZMA=y
CONFIG_XZ=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_MSCC=y
diff --git a/configs/mscc_luton_defconfig b/configs/mscc_luton_defconfig
index 7154e97..7c94a76 100644
--- a/configs/mscc_luton_defconfig
+++ b/configs/mscc_luton_defconfig
@@ -69,3 +69,5 @@ CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MSCC_BB_SPI=y
CONFIG_LZMA=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_MSCC=y
diff --git a/configs/mscc_ocelot_defconfig b/configs/mscc_ocelot_defconfig
index fb6a5bd..7d9abb6 100644
--- a/configs/mscc_ocelot_defconfig
+++ b/configs/mscc_ocelot_defconfig
@@ -69,3 +69,5 @@ CONFIG_SYS_NS16550=y
