[U-Boot] [PATCH 1/2] drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl

[Shengzhou Liu]

The clk_adjust is of SDRAM_CLK_CNTL[5:8] 4-bits on MPC85xx and P-series,
but is of SDRAM_CLK_CNTL[5:9] 5-bits on T-series and LS-series SoCs.
We should update it to adapt the case that clk_adjust is odd data.

Signed-off-by: Shengzhou Liu 
---
 drivers/ddr/fsl/ctrl_regs.c | 11 +--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 9073917..b26269c 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -1835,10 +1835,17 @@ static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t 
*ddr,
/* Per FSL Application Note: AN2805 */
ss_en = 1;
 #endif
-   clk_adjust = popts->clk_adjust;
+   if (fsl_ddr_get_version(0) >= 0x40701) {
+   /* clk_adjust in 5-bits on T-series and LS-series */
+   clk_adjust = (popts->clk_adjust & 0x1F) << 22;
+   } else {
+   /* clk_adjust in 4-bits on earlier MPC85xx and P-series */
+   clk_adjust = (popts->clk_adjust & 0xF) << 23;
+   }
+
ddr->ddr_sdram_clk_cntl = (0
   | ((ss_en & 0x1) << 31)
-  | ((clk_adjust & 0xF) << 23)
+  | clk_adjust
   );
debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
 }
-- 
2.1.0.27.g96db324

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Re: [U-Boot] [PATCH 1/2] drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl

[Shengzhou Liu]

> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: Tuesday, May 17, 2016 12:55 AM
> To: Shengzhou Liu ; u-boot@lists.denx.de
> Subject: Re: [PATCH 1/2] drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl

> 
> Shengzhou,
> 
> Your understanding is correct. However, we have done analysis that the
> additional bit is not used for finer adjustment. So unless you have a case
> requiring values in the middle, I suggest to keep current code.
> 
> York

York

On LS1046RDB, the clk_adj is 9, an odd instead of even data, so we have to 
update it, and there will be more new boards in future with possibly odd 
clk_adj.

Shengzhou
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Re: [U-Boot] [PATCH 1/2] drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl

[York Sun]

On 05/30/2016 08:18 PM, Shengzhou Liu wrote:
> 
>> -Original Message-
>> From: York Sun [mailto:york@nxp.com]
>> Sent: Tuesday, May 17, 2016 12:55 AM
>> To: Shengzhou Liu ; u-boot@lists.denx.de
>> Subject: Re: [PATCH 1/2] drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl
> 
>>
>> Shengzhou,
>>
>> Your understanding is correct. However, we have done analysis that the
>> additional bit is not used for finer adjustment. So unless you have a case
>> requiring values in the middle, I suggest to keep current code.
>>
>> York
> 
> York
> 
> On LS1046RDB, the clk_adj is 9, an odd instead of even data, so we have to 
> update it, and there will be more new boards in future with possibly odd 
> clk_adj.
> 

Shengzhou,

If you have to use an odd number for clk_adj, we can go ahead to merge these
patches. In my experience, clk_adj is very forgivable. If you have only one
value works, there is probably something wrong.

York


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Re: [U-Boot] [PATCH 1/2] drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl

[Shengzhou Liu]

> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: Wednesday, June 01, 2016 12:04 AM
> To: Shengzhou Liu ; u-boot@lists.denx.de
> Shengzhou,
> 
> If you have to use an odd number for clk_adj, we can go ahead to merge
> these patches. In my experience, clk_adj is very forgivable. If you have only
> one value works, there is probably something wrong.
> 
> York
> 
York, 
The odd clk_adj = 9  is the optimal with timing centralization, maybe it work  
if set it to 8, but not the optimal.
Theoretically we should have the actual value instead of dividing 2 to avoid 
confusion for customers.
Shengzhou
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Re: [U-Boot] [PATCH 1/2] drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl

[York Sun]

On 05/31/2016 10:12 PM, Shengzhou Liu wrote:
>> -Original Message-
>> From: York Sun [mailto:york@nxp.com]
>> Sent: Wednesday, June 01, 2016 12:04 AM
>> To: Shengzhou Liu ; u-boot@lists.denx.de
>> Shengzhou,
>>
>> If you have to use an odd number for clk_adj, we can go ahead to merge
>> these patches. In my experience, clk_adj is very forgivable. If you have only
>> one value works, there is probably something wrong.
>>
>> York
>>
> York, 
> The odd clk_adj = 9  is the optimal with timing centralization, maybe it work 
>  if set it to 8, but not the optimal.
> Theoretically we should have the actual value instead of dividing 2 to avoid 
> confusion for customers.
> Shengzhou
> 

OK. Thanks for the explanation.

York
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Re: [U-Boot] [PATCH 1/2] drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl

[York Sun]

On 05/03/2016 07:30 PM, Shengzhou Liu wrote:
> The clk_adjust is of SDRAM_CLK_CNTL[5:8] 4-bits on MPC85xx and P-series,
> but is of SDRAM_CLK_CNTL[5:9] 5-bits on T-series and LS-series SoCs.
> We should update it to adapt the case that clk_adjust is odd data.
> 
> Signed-off-by: Shengzhou Liu 
> ---
>  drivers/ddr/fsl/ctrl_regs.c | 11 +--
>  1 file changed, 9 insertions(+), 2 deletions(-)
> 

Applied to fsl-qoriq master branch. Awaiting upstream.
Thanks.

York

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Re: [U-Boot] [PATCH 1/2] drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl

[York Sun]

On 05/03/2016 07:30 PM, Shengzhou Liu wrote:
> The clk_adjust is of SDRAM_CLK_CNTL[5:8] 4-bits on MPC85xx and P-series,
> but is of SDRAM_CLK_CNTL[5:9] 5-bits on T-series and LS-series SoCs.
> We should update it to adapt the case that clk_adjust is odd data.
> 
> Signed-off-by: Shengzhou Liu 
> ---
>  drivers/ddr/fsl/ctrl_regs.c | 11 +--
>  1 file changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
> index 9073917..b26269c 100644
> --- a/drivers/ddr/fsl/ctrl_regs.c
> +++ b/drivers/ddr/fsl/ctrl_regs.c
> @@ -1835,10 +1835,17 @@ static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t 
> *ddr,
>   /* Per FSL Application Note: AN2805 */
>   ss_en = 1;
>  #endif
> - clk_adjust = popts->clk_adjust;
> + if (fsl_ddr_get_version(0) >= 0x40701) {
> + /* clk_adjust in 5-bits on T-series and LS-series */
> + clk_adjust = (popts->clk_adjust & 0x1F) << 22;
> + } else {
> + /* clk_adjust in 4-bits on earlier MPC85xx and P-series */
> + clk_adjust = (popts->clk_adjust & 0xF) << 23;
> + }
> +
>   ddr->ddr_sdram_clk_cntl = (0
>  | ((ss_en & 0x1) << 31)
> -| ((clk_adjust & 0xF) << 23)
> +| clk_adjust
>  );
>   debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
>  }
> 

Shengzhou,

Your understanding is correct. However, we have done analysis that the
additional bit is not used for finer adjustment. So unless you have a case
requiring values in the middle, I suggest to keep current code.

York
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