Re: [U-Boot] [PATCH 1/4] dm: spi: add BCM63xx HSSPI driver

2017-05-31 Thread Simon Glass 
Hi Alvaro,

On 23 May 2017 at 13:18, Álvaro Fernández Rojas  wrote:
> This driver is a simplified version of linux/drivers/spi/spi-bcm63xx-hsspi.c
>
> Signed-off-by: Álvaro Fernández Rojas 
> ---
>  drivers/spi/Kconfig |   8 +
>  drivers/spi/Makefile|   1 +
>  drivers/spi/bcm63xx_hsspi.c | 392 
> 
>  3 files changed, 401 insertions(+)
>  create mode 100644 drivers/spi/bcm63xx_hsspi.c

Reviewed-by: Simon Glass 

Suggest you add error checking to clk_enable(), etc. and split
bcm63xx_hsspi_xfer() into a few subparts as it is very long.

Regards,
Simon
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 1/4] dm: spi: add BCM63xx HSSPI driver

2017-05-23 Thread Álvaro Fernández Rojas 
This driver is a simplified version of linux/drivers/spi/spi-bcm63xx-hsspi.c

Signed-off-by: Álvaro Fernández Rojas 
---
 drivers/spi/Kconfig |   8 +
 drivers/spi/Makefile|   1 +
 drivers/spi/bcm63xx_hsspi.c | 392 
 3 files changed, 401 insertions(+)
 create mode 100644 drivers/spi/bcm63xx_hsspi.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index e452223..a67c05f 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -40,6 +40,14 @@ config ATMEL_SPI
  many AT32 (AVR32) and AT91 (ARM) chips. This driver can be
  used to access the SPI Flash, such as AT25DF321.
 
+config BCM6328_HSSPI
+   bool "BCM6328 HSSPI driver"
+   depends on ARCH_BMIPS
+   help
+ Enable the BCM6328 HSSPI driver. This driver can be used to
+ access the SPI NOR flash on platforms embedding this Broadcom
+ SPI core.
+
 choice
prompt "BCM63xx SPI driver"
depends on ARCH_BMIPS
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index c9ba648..a12a354 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
 obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
 obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
 obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
+obj-$(CONFIG_BCM6328_HSSPI) += bcm63xx_hsspi.o
 obj-$(CONFIG_BCM6338_SPI)$(CONFIG_BCM6358_SPI) += bcm63xx_spi.o
 obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
 obj-$(CONFIG_CF_SPI) += cf_spi.o
diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c
new file mode 100644
index 000..bdd2e3e
--- /dev/null
+++ b/drivers/spi/bcm63xx_hsspi.c
@@ -0,0 +1,392 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas 
+ *
+ * Derived from linux/drivers/spi/spi-bcm63xx-hsspi.c:
+ * Copyright (C) 2000-2010 Broadcom Corporation
+ * Copyright (C) 2012-2013 Jonas Gorski 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SPI_PP_SEL 0
+
+#define SPI_MAX_SYNC_CLOCK 3000
+
+/* SPI Control register */
+#define SPI_CTL_REG0x000
+#define SPI_CTL_CS_POL_SHIFT   0
+#define SPI_CTL_CS_POL_MASK(0xff << SPI_CTL_CS_POL_SHIFT)
+#define SPI_CTL_CLK_GATE_SHIFT 16
+#define SPI_CTL_CLK_GATE_MASK  (1 << SPI_CTL_CLK_GATE_SHIFT)
+#define SPI_CTL_CLK_POL_SHIFT  17
+#define SPI_CTL_CLK_POL_MASK   (1 << SPI_CTL_CLK_POL_SHIFT)
+
+/* SPI Interrupts registers */
+#define SPI_IR_STAT_REG0x008
+#define SPI_IR_ST_MASK_REG 0x00c
+#define SPI_IR_MASK_REG0x010
+
+#define SPI_IR_CLEAR_ALL   0xff001f1f
+
+/* SPI Ping-Pong Command registers */
+#define SPI_PP_CMD_REG (0x080 + (0x40 * (SPI_PP_SEL)) + 0x00)
+#define SPI_PP_CMD_OP_SHIFT0
+#define SPI_PP_CMD_OP_START(0x1 << SPI_PP_CMD_OP_SHIFT)
+#define SPI_PP_CMD_PFL_SHIFT   8
+#define SPI_PP_CMD_PFL_MASK(0x7 << SPI_PP_CMD_PFL_SHIFT)
+#define SPI_PP_CMD_SLAVE_SHIFT 12
+#define SPI_PP_CMD_SLAVE_MASK  (0x7 << SPI_PP_CMD_SLAVE_SHIFT)
+
+/* SPI Ping-Pong Status registers */
+#define SPI_PP_STAT_REG(0x080 + (0x40 * (SPI_PP_SEL)) 
+ 0x04)
+#define SPI_PP_STAT_SRCBUSY_SHIFT  1
+#define SPI_PP_STAT_SRCBUSY_MASK   (1 << SPI_PP_STAT_SRCBUSY_SHIFT)
+
+/* SPI Profile Clock registers */
+#define SPI_PFL_CLK_REG(x) (0x100 + (0x20 * (x)) + 0x00)
+#define SPI_PFL_CLK_FREQ_SHIFT 0
+#define SPI_PFL_CLK_FREQ_MASK  (0x3fff << SPI_PFL_CLK_FREQ_SHIFT)
+#define SPI_PFL_CLK_RSTLOOP_SHIFT  15
+#define SPI_PFL_CLK_RSTLOOP_MASK   (1 << SPI_PFL_CLK_RSTLOOP_SHIFT)
+
+/* SPI Profile Signal registers */
+#define SPI_PFL_SIG_REG(x) (0x100 + (0x20 * (x)) + 0x04)
+#define SPI_PFL_SIG_LATCHRIS_SHIFT 12
+#define SPI_PFL_SIG_LATCHRIS_MASK  (1 << SPI_PFL_SIG_LATCHRIS_SHIFT)
+#define SPI_PFL_SIG_LAUNCHRIS_SHIFT13
+#define SPI_PFL_SIG_LAUNCHRIS_MASK (1 << SPI_PFL_SIG_LAUNCHRIS_SHIFT)
+#define SPI_PFL_SIG_ASYNCIN_SHIFT  16
+#define SPI_PFL_SIG_ASYNCIN_MASK   (1 << SPI_PFL_SIG_ASYNCIN_SHIFT)
+
+/* SPI Profile Mode registers */
+#define SPI_PFL_MODE_REG(x)(0x100 + (0x20 * (x)) + 0x08)
+#define SPI_PFL_MODE_FILL_SHIFT0
+#define SPI_PFL_MODE_FILL_MASK (0xff << SPI_PFL_MODE_FILL_SHIFT)
+#define SPI_PFL_MODE_MDRDSZ_SHIFT  16
+#define SPI_PFL_MODE_MDRDSZ_MASK   (1 << SPI_PFL_MODE_MDRDSZ_SHIFT)
+#define SPI_PFL_MODE_MDWRSZ_SHIFT  18
+#define SPI_PFL_MODE_MDWRSZ_MASK   (1 << SPI_PFL_MODE_MDWRSZ_SHIFT)
+#define SPI_PFL_MODE_3WIRE_SHIFT   20
+#define SPI_PFL_MODE_3WIRE_MASK(1 << SPI_PFL_MODE_3WIRE_SHIFT)
+
+/* SPI Ping-Pong