Re: [U-Boot] [PATCH 1/5] arm64: a37xx: populate pcie memory region

[Stefan Roese]

On 26.03.2018 09:57, m...@marvell.com wrote:

From: Wilson Ding 

This patch added a new region of 32MiB AT 0xe800.
to Armada37x0's memory map. This region is supposed to
be mapped in MMU in order to enable the access to the
PCI I/O or MEM resources.

Signed-off-by: Wilson Ding 
Reviewed-on: http://vgitil04.il.marvell.com:8080/38724
Tested-by: iSoC Platform CI 
Reviewed-by: Victor Gu 
Signed-off-by: Ken Ma 
Cc: Simon Glass 
Cc: Stefan Roese 
---
  arch/arm/mach-mvebu/armada3700/cpu.c | 8 
  1 file changed, 8 insertions(+)

diff --git a/arch/arm/mach-mvebu/armada3700/cpu.c 
b/arch/arm/mach-mvebu/armada3700/cpu.c
index 6499eec..cfe4469 100644
--- a/arch/arm/mach-mvebu/armada3700/cpu.c
+++ b/arch/arm/mach-mvebu/armada3700/cpu.c
@@ -46,6 +46,14 @@ static struct mm_region mvebu_mem_map[] = {
 PTE_BLOCK_NON_SHARE
},
{
+   /* PCI regions */
+   .phys = 0xe800UL,
+   .virt = 0xe800UL,
+   .size = 0x0200UL,   /* 32MiB master PCI space */
+   .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+PTE_BLOCK_NON_SHARE
+   },
+   {
/* List terminator */
0,
}



Complete series applied to u-boot-marvell/master.

Thanks,
Stefan
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[U-Boot] [PATCH 1/5] arm64: a37xx: populate pcie memory region

[make]

From: Wilson Ding 

This patch added a new region of 32MiB AT 0xe800.
to Armada37x0's memory map. This region is supposed to
be mapped in MMU in order to enable the access to the
PCI I/O or MEM resources.

Signed-off-by: Wilson Ding 
Reviewed-on: http://vgitil04.il.marvell.com:8080/38724
Tested-by: iSoC Platform CI 
Reviewed-by: Victor Gu 
Signed-off-by: Ken Ma 
Cc: Simon Glass 
Cc: Stefan Roese 
---
 arch/arm/mach-mvebu/armada3700/cpu.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/mach-mvebu/armada3700/cpu.c 
b/arch/arm/mach-mvebu/armada3700/cpu.c
index 6499eec..cfe4469 100644
--- a/arch/arm/mach-mvebu/armada3700/cpu.c
+++ b/arch/arm/mach-mvebu/armada3700/cpu.c
@@ -46,6 +46,14 @@ static struct mm_region mvebu_mem_map[] = {
 PTE_BLOCK_NON_SHARE
},
{
+   /* PCI regions */
+   .phys = 0xe800UL,
+   .virt = 0xe800UL,
+   .size = 0x0200UL,   /* 32MiB master PCI space */
+   .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+PTE_BLOCK_NON_SHARE
+   },
+   {
/* List terminator */
0,
}
-- 
1.9.1

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