Re: [U-Boot] [PATCH 10/13] x86: Enable mrc cache for bayleybay and minnowmax

[Simon Glass]

On 11 October 2015 at 22:37, Bin Meng  wrote:
> Now that we have added MRC cache for Intel FSP and BayTrail codes,
> enable it for all BayTrail boards (Bayley Bay and Minnow Max).
>
> Note it turns out that FSP for Intel Atom E6xx does not produce
> the HOB for NV storage, so we don't have such functionality on
> Intel Crown Bay board.
>
> Signed-off-by: Bin Meng 
> ---
>
>  arch/x86/dts/bayleybay.dts  | 6 ++
>  arch/x86/dts/minnowmax.dts  | 6 ++
>  configs/bayleybay_defconfig | 1 +
>  configs/minnowmax_defconfig | 1 +
>  doc/README.x86  | 1 +
>  5 files changed, 15 insertions(+)

Acked-by: Simon Glass 
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Re: [U-Boot] [PATCH 10/13] x86: Enable mrc cache for bayleybay and minnowmax

[Simon Glass]

On 18 October 2015 at 14:27, Simon Glass  wrote:
> On 11 October 2015 at 22:37, Bin Meng  wrote:
>> Now that we have added MRC cache for Intel FSP and BayTrail codes,
>> enable it for all BayTrail boards (Bayley Bay and Minnow Max).
>>
>> Note it turns out that FSP for Intel Atom E6xx does not produce
>> the HOB for NV storage, so we don't have such functionality on
>> Intel Crown Bay board.
>>
>> Signed-off-by: Bin Meng 
>> ---
>>
>>  arch/x86/dts/bayleybay.dts  | 6 ++
>>  arch/x86/dts/minnowmax.dts  | 6 ++
>>  configs/bayleybay_defconfig | 1 +
>>  configs/minnowmax_defconfig | 1 +
>>  doc/README.x86  | 1 +
>>  5 files changed, 15 insertions(+)
>
> Acked-by: Simon Glass 

Applied to u-boot-x86, thanks!
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[U-Boot] [PATCH 10/13] x86: Enable mrc cache for bayleybay and minnowmax

[Bin Meng]

Now that we have added MRC cache for Intel FSP and BayTrail codes,
enable it for all BayTrail boards (Bayley Bay and Minnow Max).

Note it turns out that FSP for Intel Atom E6xx does not produce
the HOB for NV storage, so we don't have such functionality on
Intel Crown Bay board.

Signed-off-by: Bin Meng 
---

 arch/x86/dts/bayleybay.dts  | 6 ++
 arch/x86/dts/minnowmax.dts  | 6 ++
 configs/bayleybay_defconfig | 1 +
 configs/minnowmax_defconfig | 1 +
 doc/README.x86  | 1 +
 5 files changed, 15 insertions(+)

diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index d646987..52d0999 100644
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -68,9 +68,15 @@
#size-cells = <0>;
compatible = "intel,ich-spi";
spi-flash@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
reg = <0>;
compatible = "winbond,w25q64dw", "spi-flash";
memory-map = <0xff80 0x0080>;
+   rw-mrc-cache {
+   label = "rw-mrc-cache";
+   reg = <0x006e 0x0001>;
+   };
};
};
 
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index e917f0f..b03f987 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -273,9 +273,15 @@
#size-cells = <0>;
compatible = "intel,ich-spi";
spi-flash@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
reg = <0>;
compatible = "stmicro,n25q064a", "spi-flash";
memory-map = <0xff80 0x0080>;
+   rw-mrc-cache {
+   label = "rw-mrc-cache";
+   reg = <0x006f 0x0001>;
+   };
};
};
 
diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig
index 56316ee..fc40da8 100644
--- a/configs/bayleybay_defconfig
+++ b/configs/bayleybay_defconfig
@@ -3,6 +3,7 @@ CONFIG_VENDOR_INTEL=y
 CONFIG_DEFAULT_DEVICE_TREE="bayleybay"
 CONFIG_TARGET_BAYLEYBAY=y
 CONFIG_HAVE_INTEL_ME=y
+CONFIG_ENABLE_MRC_CACHE=y
 CONFIG_SMP=y
 CONFIG_HAVE_VGA_BIOS=y
 CONFIG_VGA_BIOS_ADDR=0xfffa
diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig
index 0d5bd4e..8f99f0e 100644
--- a/configs/minnowmax_defconfig
+++ b/configs/minnowmax_defconfig
@@ -3,6 +3,7 @@ CONFIG_VENDOR_INTEL=y
 CONFIG_DEFAULT_DEVICE_TREE="minnowmax"
 CONFIG_TARGET_MINNOWMAX=y
 CONFIG_HAVE_INTEL_ME=y
+CONFIG_ENABLE_MRC_CACHE=y
 CONFIG_SMP=y
 CONFIG_HAVE_VGA_BIOS=y
 CONFIG_GENERATE_PIRQ_TABLE=y
diff --git a/doc/README.x86 b/doc/README.x86
index a9d0e0f..1271e5e 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -190,6 +190,7 @@ Offset   Description Controlling config
 00   descriptor.bin  Hard-coded to 0 in ifdtool
 001000   me.bin  Set by the descriptor
 50   
+6f   MRC cache   CONFIG_ENABLE_MRC_CACHE
 70   u-boot-dtb.bin  CONFIG_SYS_TEXT_BASE
 79   vga.bin CONFIG_VGA_BIOS_ADDR
 7c   fsp.bin CONFIG_FSP_ADDR
-- 
1.8.2.1

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