Since FSMC is a standard IP and it supports different memory interfaces the FSMC
is supported independent of spear platform and spear is configured to use that
driver for interfacing with the NAND device
Signed-off-by: Vipin Kumar
---
arch/arm/include/asm/arch-spear/hardware.h |8 +-
arch/arm/include/asm/arch-spear/spr_nand.h | 57 -
board/spear/spear300/spear300.c|5 +-
board/spear/spear310/spear310.c|5 +-
board/spear/spear320/spear320.c|5 +-
board/spear/spear600/spear600.c|5 +-
drivers/mtd/nand/Makefile |1 -
drivers/mtd/nand/spr_nand.c| 124
include/configs/spear-common.h |2 +-
include/configs/spear3xx.h |4 +
include/configs/spear6xx.h |3 +
11 files changed, 24 insertions(+), 195 deletions(-)
delete mode 100644 arch/arm/include/asm/arch-spear/spr_nand.h
delete mode 100644 drivers/mtd/nand/spr_nand.c
diff --git a/arch/arm/include/asm/arch-spear/hardware.h
b/arch/arm/include/asm/arch-spear/hardware.h
index 9f1e154..52037b6 100644
--- a/arch/arm/include/asm/arch-spear/hardware.h
+++ b/arch/arm/include/asm/arch-spear/hardware.h
@@ -38,15 +38,15 @@
#if defined(CONFIG_SPEAR600)
#define CONFIG_SYS_I2C_BASE(0xD020)
-#define CONFIG_SPEAR_FSMCBASE (0xD180)
+#define CONFIG_SYS_FSMC_BASE (0xD180)
#elif defined(CONFIG_SPEAR300)
#define CONFIG_SYS_I2C_BASE(0xD018)
-#define CONFIG_SPEAR_FSMCBASE (0x9400)
+#define CONFIG_SYS_FSMC_BASE (0x9400)
#elif defined(CONFIG_SPEAR310)
#define CONFIG_SYS_I2C_BASE(0xD018)
-#define CONFIG_SPEAR_FSMCBASE (0x4400)
+#define CONFIG_SYS_FSMC_BASE (0x4400)
#undef CONFIG_SYS_NAND_CLE
#undef CONFIG_SYS_NAND_ALE
@@ -63,7 +63,7 @@
#elif defined(CONFIG_SPEAR320)
#define CONFIG_SYS_I2C_BASE(0xD018)
-#define CONFIG_SPEAR_FSMCBASE (0x4C00)
+#define CONFIG_SYS_FSMC_BASE (0x4C00)
#define CONFIG_SPEAR_EMIBASE (0x4000)
#define CONFIG_SPEAR_RASBASE (0xB300)
diff --git a/arch/arm/include/asm/arch-spear/spr_nand.h
b/arch/arm/include/asm/arch-spear/spr_nand.h
deleted file mode 100644
index 2b63dc7..000
--- a/arch/arm/include/asm/arch-spear/spr_nand.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.ku...@st.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __SPR_NAND_H__
-#define __SPR_NAND_H__
-
-struct fsmc_regs {
- u32 reserved_1[0x10];
- u32 genmemctrl_pc;
- u32 reserved_2;
- u32 genmemctrl_comm;
- u32 genmemctrl_attrib;
- u32 reserved_3;
- u32 genmemctrl_ecc;
-};
-
-/* genmemctrl_pc register definitions */
-#define FSMC_RESET (1 << 0)
-#define FSMC_WAITON(1 << 1)
-#define FSMC_ENABLE(1 << 2)
-#define FSMC_DEVTYPE_NAND (1 << 3)
-#define FSMC_DEVWID_8 (0 << 4)
-#define FSMC_DEVWID_16 (1 << 4)
-#define FSMC_ECCEN (1 << 6)
-#define FSMC_ECCPLEN_512 (0 << 7)
-#define FSMC_ECCPLEN_256 (1 << 7)
-#define FSMC_TCLR_1(1 << 9)
-#define FSMC_TAR_1 (1 << 13)
-
-/* genmemctrl_comm register definitions */
-#define FSMC_TSET_0(0 << 0)
-#define FSMC_TWAIT_6 (6 << 8)
-#define FSMC_THOLD_4 (4 << 16)
-#define FSMC_THIZ_1(1 << 24)
-
-extern int spear_nand_init(struct nand_chip *nand);
-#endif
diff --git a/board/spear/spear300/spear300.c b/board/spear/spear300/spear300.c
index e58792a..33f0983 100644
--- a/board/spear/spear300/spear300.c
+++ b/board/spear/spear300/spear300.c
@@ -28,7 +28,8 @@
#include
#include
#include
-#include
+
+int fsmc_nand_init(struct nand_chip *nand);
int board_init(void)
{
@@ -52,7 +53,7 @@ int board_nand_init(struct nand_chip *nand)
((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
MISC_SOCCFG31))
