[U-Boot] [PATCH 12/19] fix: nand: pxa3xx: Add SoC-specific enable function
From: Igal Liberman
Add SoC-dependent function to the NAND driver for selecting
NAND interface in DEVBUS MUX register.
This selection is done in the BootROM if the boot device is NAND,
but may be missing othervise.
The NAND is selected only if it is enabled in the DT file.
This patch is fixing NAND access problems for configurations
that use non-NAND devices for boot (like SPI).
Signed-off-by: Igal Liberman
Signed-off-by: Konstantin Porotchkin
Signed-off-by: David Sniatkiwicz
Cc: Stefan Roese
Cc: Simon Glass
---
arch/arm/dts/armada-cp110-master.dtsi | 7 +++-
arch/arm/mach-mvebu/armada8k/cpu.c | 18 -
arch/arm/mach-mvebu/armada8k/soc.c | 30 ++
arch/arm/mach-mvebu/cpu.c | 12 +-
arch/arm/mach-mvebu/include/mach/cpu.h | 3 +-
drivers/mtd/nand/pxa3xx_nand.c | 74 +-
6 files changed, 114 insertions(+), 30 deletions(-)
diff --git a/arch/arm/dts/armada-cp110-master.dtsi
b/arch/arm/dts/armada-cp110-master.dtsi
index 551d00d..02cee94 100644
--- a/arch/arm/dts/armada-cp110-master.dtsi
+++ b/arch/arm/dts/armada-cp110-master.dtsi
@@ -276,7 +276,12 @@
cpm_nand: nand@72 {
compatible = "marvell,mvebu-pxa3xx-nand";
- reg = <0x72 0x100>;
+ reg = <0x72 0x100>,
+ <0x440700 0x20>,
+ <0x440208 0x20>;
+ reg-names = "ctrl_base",
+ "flash_clock",
+ "dev_mux";
#address-cells = <1>;
clocks = <&cpm_syscon0 1 2>;
diff --git a/arch/arm/mach-mvebu/armada8k/cpu.c
b/arch/arm/mach-mvebu/armada8k/cpu.c
index dd028e5..77e9400 100644
--- a/arch/arm/mach-mvebu/armada8k/cpu.c
+++ b/arch/arm/mach-mvebu/armada8k/cpu.c
@@ -109,24 +109,6 @@ void reset_cpu(ulong ignored)
writel(reg, RFU_GLOBAL_SW_RST);
}
-/*
- * TODO - implement this functionality using platform
- *clock driver once it gets available
- * Return NAND clock in Hz
- */
-u32 mvebu_get_nand_clock(void)
-{
- unsigned long NAND_FLASH_CLK_CTRL = 0xF2440700UL;
- unsigned long NF_CLOCK_SEL_MASK = 0x1;
- u32 reg;
-
- reg = readl(NAND_FLASH_CLK_CTRL);
- if (reg & NF_CLOCK_SEL_MASK)
- return 400 * 100;
- else
- return 250 * 100;
-}
-
#if defined(CONFIG_DISPLAY_BOARDINFO)
int print_cpuinfo(void)
{
diff --git a/arch/arm/mach-mvebu/armada8k/soc.c
b/arch/arm/mach-mvebu/armada8k/soc.c
index 511c734..faf1405 100644
--- a/arch/arm/mach-mvebu/armada8k/soc.c
+++ b/arch/arm/mach-mvebu/armada8k/soc.c
@@ -14,6 +14,10 @@
#define SW_REV_STATUS_OFFSET 16
#define SW_REV_STATUS_MASK 0xf
+#define NF_CLOCK_SEL_MASK 0x1
+#define SOC_MUX_NAND_EN_MASK 0x1
+#define CLOCK_1Mhz 100
+
struct mochi_module {
u32 module_type;
u32 module_rev;
@@ -128,3 +132,29 @@ void soc_print_device_info(void)
else
printf("CP%x-A%d\n", cp_type, cp_rev);
}
+#ifdef CONFIG_NAND_PXA3XX
+/* Return NAND clock in Hz */
+u32 mvebu_get_nand_clock(void __iomem *nand_flash_clk_ctrl_reg)
+{
+ u32 reg;
+
+ if (!nand_flash_clk_ctrl_reg)
+ return 0;
+
+ reg = readl(nand_flash_clk_ctrl_reg);
+ if (reg & NF_CLOCK_SEL_MASK)
+ return 400 * CLOCK_1Mhz;
+ else
+ return 250 * CLOCK_1Mhz;
+}
+
+/* Select NAND in the device bus multiplexer */
+void mvebu_nand_select(void __iomem *soc_dev_multiplex_reg)
+{
+ if (!soc_dev_multiplex_reg)
+ return;
+
+ setbits_le32(soc_dev_multiplex_reg, SOC_MUX_NAND_EN_MASK);
+}
+#endif
+
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index 0d2d398..b1d1b1d 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -15,6 +15,8 @@
#define DDR_BASE_CS_OFF(n) (0x + ((n) << 3))
#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
+#define SOC_MUX_NAND_EN_MASK 0x1
+
static struct mbus_win windows[] = {
/* SPI */
{ MBUS_SPI_BASE, MBUS_SPI_SIZE,
@@ -465,7 +467,7 @@ int arch_cpu_init(void)
}
#endif /* CONFIG_ARCH_CPU_INIT */
-u32 mvebu_get_nand_clock(void)
+u32 mvebu_get_nand_clock(void __iomem *unused)
{
u32 reg;
@@ -479,6 +481,14 @@ u32 mvebu_get_nand_clock(void)
NAND_ECC_DIVCKL_RATIO_MASK) >> NAND_ECC_DIVCKL_RATIO_OFFS);
}
+void mvebu_nand_select(void __iomem *soc_dev_multiplex_reg)
+{
+ if (!soc_dev_multiplex_reg)
+ return;
+
+ setbits_le32(soc_dev_multiplex_reg, SOC_MUX_NAND_EN_MASK);
+}
+
/*
* SOC specific misc init
*/
diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h
b/arch/arm/mach-mvebu/include/mach/cpu.h
index d
Re: [U-Boot] [PATCH 12/19] fix: nand: pxa3xx: Add SoC-specific enable function
On 29.08.2018 10:56, kos...@marvell.com wrote:
From: Igal Liberman
Add SoC-dependent function to the NAND driver for selecting
NAND interface in DEVBUS MUX register.
This selection is done in the BootROM if the boot device is NAND,
but may be missing othervise.
The NAND is selected only if it is enabled in the DT file.
This patch is fixing NAND access problems for configurations
that use non-NAND devices for boot (like SPI).
Signed-off-by: Igal Liberman
Signed-off-by: Konstantin Porotchkin
Signed-off-by: David Sniatkiwicz
Cc: Stefan Roese
Cc: Simon Glass
---
arch/arm/dts/armada-cp110-master.dtsi | 7 +++-
arch/arm/mach-mvebu/armada8k/cpu.c | 18 -
arch/arm/mach-mvebu/armada8k/soc.c | 30 ++
arch/arm/mach-mvebu/cpu.c | 12 +-
arch/arm/mach-mvebu/include/mach/cpu.h | 3 +-
drivers/mtd/nand/pxa3xx_nand.c | 74 +-
6 files changed, 114 insertions(+), 30 deletions(-)
diff --git a/arch/arm/dts/armada-cp110-master.dtsi
b/arch/arm/dts/armada-cp110-master.dtsi
index 551d00d..02cee94 100644
--- a/arch/arm/dts/armada-cp110-master.dtsi
+++ b/arch/arm/dts/armada-cp110-master.dtsi
@@ -276,7 +276,12 @@
cpm_nand: nand@72 {
compatible = "marvell,mvebu-pxa3xx-nand";
- reg = <0x72 0x100>;
+ reg = <0x72 0x100>,
+ <0x440700 0x20>,
+ <0x440208 0x20>;
+ reg-names = "ctrl_base",
+ "flash_clock",
+ "dev_mux";
#address-cells = <1>;
clocks = <&cpm_syscon0 1 2>;
diff --git a/arch/arm/mach-mvebu/armada8k/cpu.c
b/arch/arm/mach-mvebu/armada8k/cpu.c
index dd028e5..77e9400 100644
--- a/arch/arm/mach-mvebu/armada8k/cpu.c
+++ b/arch/arm/mach-mvebu/armada8k/cpu.c
@@ -109,24 +109,6 @@ void reset_cpu(ulong ignored)
writel(reg, RFU_GLOBAL_SW_RST);
}
-/*
- * TODO - implement this functionality using platform
- *clock driver once it gets available
- * Return NAND clock in Hz
- */
-u32 mvebu_get_nand_clock(void)
-{
- unsigned long NAND_FLASH_CLK_CTRL = 0xF2440700UL;
- unsigned long NF_CLOCK_SEL_MASK = 0x1;
- u32 reg;
-
- reg = readl(NAND_FLASH_CLK_CTRL);
- if (reg & NF_CLOCK_SEL_MASK)
- return 400 * 100;
- else
- return 250 * 100;
-}
-
#if defined(CONFIG_DISPLAY_BOARDINFO)
int print_cpuinfo(void)
{
diff --git a/arch/arm/mach-mvebu/armada8k/soc.c
b/arch/arm/mach-mvebu/armada8k/soc.c
index 511c734..faf1405 100644
--- a/arch/arm/mach-mvebu/armada8k/soc.c
+++ b/arch/arm/mach-mvebu/armada8k/soc.c
@@ -14,6 +14,10 @@
#define SW_REV_STATUS_OFFSET 16
#define SW_REV_STATUS_MASK0xf
+#define NF_CLOCK_SEL_MASK 0x1
+#define SOC_MUX_NAND_EN_MASK 0x1
+#define CLOCK_1Mhz 100
+
struct mochi_module {
u32 module_type;
u32 module_rev;
@@ -128,3 +132,29 @@ void soc_print_device_info(void)
else
printf("CP%x-A%d\n", cp_type, cp_rev);
}
+#ifdef CONFIG_NAND_PXA3XX
+/* Return NAND clock in Hz */
+u32 mvebu_get_nand_clock(void __iomem *nand_flash_clk_ctrl_reg)
+{
+ u32 reg;
+
+ if (!nand_flash_clk_ctrl_reg)
+ return 0;
+
+ reg = readl(nand_flash_clk_ctrl_reg);
+ if (reg & NF_CLOCK_SEL_MASK)
+ return 400 * CLOCK_1Mhz;
+ else
+ return 250 * CLOCK_1Mhz;
+}
+
+/* Select NAND in the device bus multiplexer */
+void mvebu_nand_select(void __iomem *soc_dev_multiplex_reg)
+{
+ if (!soc_dev_multiplex_reg)
+ return;
+
+ setbits_le32(soc_dev_multiplex_reg, SOC_MUX_NAND_EN_MASK);
+}
+#endif
+
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index 0d2d398..b1d1b1d 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -15,6 +15,8 @@
#define DDR_BASE_CS_OFF(n)(0x + ((n) << 3))
#define DDR_SIZE_CS_OFF(n)(0x0004 + ((n) << 3))
+#define SOC_MUX_NAND_EN_MASK 0x1
+
static struct mbus_win windows[] = {
/* SPI */
{ MBUS_SPI_BASE, MBUS_SPI_SIZE,
@@ -465,7 +467,7 @@ int arch_cpu_init(void)
}
#endif /* CONFIG_ARCH_CPU_INIT */
-u32 mvebu_get_nand_clock(void)
+u32 mvebu_get_nand_clock(void __iomem *unused)
{
u32 reg;
@@ -479,6 +481,14 @@ u32 mvebu_get_nand_clock(void)
NAND_ECC_DIVCKL_RATIO_MASK) >> NAND_ECC_DIVCKL_RATIO_OFFS);
}
+void mvebu_nand_select(void __iomem *soc_dev_multiplex_reg)
+{
+ if (!soc_dev_multiplex_reg)
+ return;
+
+ setbits_le32(soc_dev_multiplex_reg, SOC_MUX_NAND_EN_MASK);
+}
+
/*
* SOC specific misc init
*/
diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h
b/arch/arm/mach-mvebu/includ
Re: [U-Boot] [PATCH 12/19] fix: nand: pxa3xx: Add SoC-specific enable function
Hi Kosta,
On 19.09.18 14:34, Stefan Roese wrote:
On 29.08.2018 10:56, kos...@marvell.com wrote:
From: Igal Liberman
Add SoC-dependent function to the NAND driver for selecting
NAND interface in DEVBUS MUX register.
This selection is done in the BootROM if the boot device is NAND,
but may be missing othervise.
The NAND is selected only if it is enabled in the DT file.
This patch is fixing NAND access problems for configurations
that use non-NAND devices for boot (like SPI).
Signed-off-by: Igal Liberman
Signed-off-by: Konstantin Porotchkin
Signed-off-by: David Sniatkiwicz
Cc: Stefan Roese
Cc: Simon Glass
---
arch/arm/dts/armada-cp110-master.dtsi | 7 +++-
arch/arm/mach-mvebu/armada8k/cpu.c | 18 -
arch/arm/mach-mvebu/armada8k/soc.c | 30 ++
arch/arm/mach-mvebu/cpu.c | 12 +-
arch/arm/mach-mvebu/include/mach/cpu.h | 3 +-
drivers/mtd/nand/pxa3xx_nand.c | 74
+-
6 files changed, 114 insertions(+), 30 deletions(-)
diff --git a/arch/arm/dts/armada-cp110-master.dtsi
b/arch/arm/dts/armada-cp110-master.dtsi
index 551d00d..02cee94 100644
--- a/arch/arm/dts/armada-cp110-master.dtsi
+++ b/arch/arm/dts/armada-cp110-master.dtsi
@@ -276,7 +276,12 @@
cpm_nand: nand@72 {
compatible = "marvell,mvebu-pxa3xx-nand";
- reg = <0x72 0x100>;
+ reg = <0x72 0x100>,
+ <0x440700 0x20>,
+ <0x440208 0x20>;
+ reg-names = "ctrl_base",
+ "flash_clock",
+ "dev_mux";
#address-cells = <1>;
clocks = <&cpm_syscon0 1 2>;
diff --git a/arch/arm/mach-mvebu/armada8k/cpu.c
b/arch/arm/mach-mvebu/armada8k/cpu.c
index dd028e5..77e9400 100644
--- a/arch/arm/mach-mvebu/armada8k/cpu.c
+++ b/arch/arm/mach-mvebu/armada8k/cpu.c
@@ -109,24 +109,6 @@ void reset_cpu(ulong ignored)
writel(reg, RFU_GLOBAL_SW_RST);
}
-/*
- * TODO - implement this functionality using platform
- *clock driver once it gets available
- * Return NAND clock in Hz
- */
-u32 mvebu_get_nand_clock(void)
-{
- unsigned long NAND_FLASH_CLK_CTRL = 0xF2440700UL;
- unsigned long NF_CLOCK_SEL_MASK = 0x1;
- u32 reg;
-
- reg = readl(NAND_FLASH_CLK_CTRL);
- if (reg & NF_CLOCK_SEL_MASK)
- return 400 * 100;
- else
- return 250 * 100;
-}
-
#if defined(CONFIG_DISPLAY_BOARDINFO)
int print_cpuinfo(void)
{
diff --git a/arch/arm/mach-mvebu/armada8k/soc.c
b/arch/arm/mach-mvebu/armada8k/soc.c
index 511c734..faf1405 100644
--- a/arch/arm/mach-mvebu/armada8k/soc.c
+++ b/arch/arm/mach-mvebu/armada8k/soc.c
@@ -14,6 +14,10 @@
#define SW_REV_STATUS_OFFSET 16
#define SW_REV_STATUS_MASK 0xf
+#define NF_CLOCK_SEL_MASK 0x1
+#define SOC_MUX_NAND_EN_MASK 0x1
+#define CLOCK_1Mhz 100
+
struct mochi_module {
u32 module_type;
u32 module_rev;
@@ -128,3 +132,29 @@ void soc_print_device_info(void)
else
printf("CP%x-A%d\n", cp_type, cp_rev);
}
+#ifdef CONFIG_NAND_PXA3XX
+/* Return NAND clock in Hz */
+u32 mvebu_get_nand_clock(void __iomem *nand_flash_clk_ctrl_reg)
+{
+ u32 reg;
+
+ if (!nand_flash_clk_ctrl_reg)
+ return 0;
+
+ reg = readl(nand_flash_clk_ctrl_reg);
+ if (reg & NF_CLOCK_SEL_MASK)
+ return 400 * CLOCK_1Mhz;
+ else
+ return 250 * CLOCK_1Mhz;
+}
+
+/* Select NAND in the device bus multiplexer */
+void mvebu_nand_select(void __iomem *soc_dev_multiplex_reg)
+{
+ if (!soc_dev_multiplex_reg)
+ return;
+
+ setbits_le32(soc_dev_multiplex_reg, SOC_MUX_NAND_EN_MASK);
+}
+#endif
+
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index 0d2d398..b1d1b1d 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -15,6 +15,8 @@
#define DDR_BASE_CS_OFF(n) (0x + ((n) << 3))
#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
+#define SOC_MUX_NAND_EN_MASK 0x1
+
static struct mbus_win windows[] = {
/* SPI */
{ MBUS_SPI_BASE, MBUS_SPI_SIZE,
@@ -465,7 +467,7 @@ int arch_cpu_init(void)
}
#endif /* CONFIG_ARCH_CPU_INIT */
-u32 mvebu_get_nand_clock(void)
+u32 mvebu_get_nand_clock(void __iomem *unused)
{
u32 reg;
@@ -479,6 +481,14 @@ u32 mvebu_get_nand_clock(void)
NAND_ECC_DIVCKL_RATIO_MASK) >> NAND_ECC_DIVCKL_RATIO_OFFS);
}
+void mvebu_nand_select(void __iomem *soc_dev_multiplex_reg)
+{
+ if (!soc_dev_multiplex_reg)
+ return;
+
+ setbits_le32(soc_dev_multiplex_reg, SOC_MUX_NAND_EN_MASK);
+}
+
/*
* SOC specific misc init
*
