Re: [U-Boot] [PATCH 14/30] riscv: complete the list of exception codes

[Rick Chen]

> > > Only the first four exception codes are defined. Add the missing
> > > exception codes from the definition in RISC-V Privileged Architecture
> > > Version 1.10.
> > >
> > > Signed-off-by: Lukas Auer 
> > > ---
> > >
> > >  arch/riscv/lib/interrupts.c | 13 -
> > >  1 file changed, 12 insertions(+), 1 deletion(-)
> > >
> >
> > Reviewed-by: Bin Meng 

Reviewed-by: Rick Chen 
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Re: [U-Boot] [PATCH 14/30] riscv: complete the list of exception codes

[Bin Meng]

On Sat, Oct 20, 2018 at 6:10 AM Lukas Auer
 wrote:
>
> Only the first four exception codes are defined. Add the missing
> exception codes from the definition in RISC-V Privileged Architecture
> Version 1.10.
>
> Signed-off-by: Lukas Auer 
> ---
>
>  arch/riscv/lib/interrupts.c | 13 -
>  1 file changed, 12 insertions(+), 1 deletion(-)
>

Reviewed-by: Bin Meng 
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[U-Boot] [PATCH 14/30] riscv: complete the list of exception codes

[Lukas Auer]

Only the first four exception codes are defined. Add the missing
exception codes from the definition in RISC-V Privileged Architecture
Version 1.10.

Signed-off-by: Lukas Auer 
---

 arch/riscv/lib/interrupts.c | 13 -
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c
index 1c16980a64..3d830c3273 100644
--- a/arch/riscv/lib/interrupts.c
+++ b/arch/riscv/lib/interrupts.c
@@ -67,7 +67,18 @@ static void _exit_trap(ulong code, ulong epc, struct pt_regs 
*regs)
"Instruction access fault",
"Illegal instruction",
"Breakpoint",
-   "Load address misaligned"
+   "Load address misaligned",
+   "Load access fault",
+   "Store/AMO address misaligned",
+   "Store/AMO access fault",
+   "Environment call from U-mode",
+   "Environment call from S-mode",
+   "Reserved",
+   "Environment call from M-mode",
+   "Instruction page fault",
+   "Load page fault",
+   "Reserved",
+   "Store/AMO page fault",
};
 
printf("exception code: %ld , %s , epc %016lx , ra %016lx\n",
-- 
2.17.2

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