Re: [U-Boot] [PATCH 2/2] ARMv7: at91: enable ICache and DCache.

2014-05-16 Thread Bo Shen 

Hi Josh,

On 05/16/2014 05:17 PM, Josh Wu wrote:

diff --git a/board/atmel/sama5d3xek/sama5d3xek.c
b/board/atmel/sama5d3xek/sama5d3xek.c
index c835c12..1fc91d9 100644
--- a/board/atmel/sama5d3xek/sama5d3xek.c
+++ b/board/atmel/sama5d3xek/sama5d3xek.c
@@ -200,8 +200,12 @@ int board_init(void)
  at91_gmac_hw_init();
  #endif
  #ifdef CONFIG_LCD
-if (has_lcdc())
+if (has_lcdc()) {
  sama5d3xek_lcd_hw_init();
+
+/* Enable flushing as we enabled dcache */
+lcd_set_flush_dcache(1);


Why not implement in driver, or else, each SoC enable dcache will need
add this.


hmm, the thing is some at91 board, for example at91sam9x5ek board, not
defined CONFIG_SYS_DCACHE_OFF, that means DCache is enabled. But
actually it doesn't implement dcache_enable().
In above situation, if we implement it in driver, I can't tell whether
dcache is really enabled or not.
For this reason, I manually call lcd_set_flush_dcache(1) in the board file.
In the future if all boards (use hlcd driver) enabled dcache I will move
this function to hlcd driver.


I don't see any issue to implement this in driver, may be I am wrong? 
Can you figure out what issue you met?


Btw, if there is really have issues, can make this condition with 
CONFIG_SYS_DCACHE_OFF?



Best Regards,
Josh Wu


Best Regards,
Bo Shen
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Re: [U-Boot] [PATCH 2/2] ARMv7: at91: enable ICache and DCache.

2014-05-16 Thread Josh Wu 

Hi, Bo

Thanks for the review  ;-)

On 5/16/2014 4:29 PM, Bo Shen wrote:

Hi Josh,

On 05/16/2014 04:15 PM, Josh Wu wrote:

As SAMA5D3 is a at91 ARMv7 cpu, so we should enable LCD DCache
flush for SAMA5D3X-EK.

Signed-off-by: Josh Wu 
---
  arch/arm/cpu/armv7/at91/cpu.c   |6 ++
  board/atmel/sama5d3xek/sama5d3xek.c |6 +-
  2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/at91/cpu.c 
b/arch/arm/cpu/armv7/at91/cpu.c

index 2fbf60d..6f2164f 100644
--- a/arch/arm/cpu/armv7/at91/cpu.c
+++ b/arch/arm/cpu/armv7/at91/cpu.c
@@ -61,6 +61,12 @@ int print_cpuinfo(void)

  void enable_caches(void)
  {
+#ifndef CONFIG_SYS_ICACHE_OFF
+icache_enable();
+#endif


No need this one. Ifdef CONFIG_SYS_ICACHE_OFF, it will be disabled.


ok, good. I will remove this #if.




+#ifndef CONFIG_SYS_DCACHE_OFF
+dcache_enable();
+#endif


This will be removed too.


  }

  unsigned int get_chip_id(void)
diff --git a/board/atmel/sama5d3xek/sama5d3xek.c 
b/board/atmel/sama5d3xek/sama5d3xek.c

index c835c12..1fc91d9 100644
--- a/board/atmel/sama5d3xek/sama5d3xek.c
+++ b/board/atmel/sama5d3xek/sama5d3xek.c
@@ -200,8 +200,12 @@ int board_init(void)
  at91_gmac_hw_init();
  #endif
  #ifdef CONFIG_LCD
-if (has_lcdc())
+if (has_lcdc()) {
  sama5d3xek_lcd_hw_init();
+
+/* Enable flushing as we enabled dcache */
+lcd_set_flush_dcache(1);


Why not implement in driver, or else, each SoC enable dcache will need 
add this.


hmm, the thing is some at91 board, for example at91sam9x5ek board, not 
defined CONFIG_SYS_DCACHE_OFF, that means DCache is enabled. But 
actually it doesn't implement dcache_enable().
In above situation, if we implement it in driver, I can't tell whether 
dcache is really enabled or not.

For this reason, I manually call lcd_set_flush_dcache(1) in the board file.
In the future if all boards (use hlcd driver) enabled dcache I will move 
this function to hlcd driver.


Best Regards,
Josh Wu




+}
  #endif
  return 0;
  }



Best Regards,
Bo Shen



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Re: [U-Boot] [PATCH 2/2] ARMv7: at91: enable ICache and DCache.

2014-05-16 Thread Bo Shen 

Hi Josh,

On 05/16/2014 04:15 PM, Josh Wu wrote:

As SAMA5D3 is a at91 ARMv7 cpu, so we should enable LCD DCache
flush for SAMA5D3X-EK.

Signed-off-by: Josh Wu 
---
  arch/arm/cpu/armv7/at91/cpu.c   |6 ++
  board/atmel/sama5d3xek/sama5d3xek.c |6 +-
  2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/at91/cpu.c b/arch/arm/cpu/armv7/at91/cpu.c
index 2fbf60d..6f2164f 100644
--- a/arch/arm/cpu/armv7/at91/cpu.c
+++ b/arch/arm/cpu/armv7/at91/cpu.c
@@ -61,6 +61,12 @@ int print_cpuinfo(void)

  void enable_caches(void)
  {
+#ifndef CONFIG_SYS_ICACHE_OFF
+   icache_enable();
+#endif


No need this one. Ifdef CONFIG_SYS_ICACHE_OFF, it will be disabled.


+#ifndef CONFIG_SYS_DCACHE_OFF
+   dcache_enable();
+#endif
  }

  unsigned int get_chip_id(void)
diff --git a/board/atmel/sama5d3xek/sama5d3xek.c 
b/board/atmel/sama5d3xek/sama5d3xek.c
index c835c12..1fc91d9 100644
--- a/board/atmel/sama5d3xek/sama5d3xek.c
+++ b/board/atmel/sama5d3xek/sama5d3xek.c
@@ -200,8 +200,12 @@ int board_init(void)
at91_gmac_hw_init();
  #endif
  #ifdef CONFIG_LCD
-   if (has_lcdc())
+   if (has_lcdc()) {
sama5d3xek_lcd_hw_init();
+
+   /* Enable flushing as we enabled dcache */
+   lcd_set_flush_dcache(1);


Why not implement in driver, or else, each SoC enable dcache will need 
add this.



+   }
  #endif
return 0;
  }



Best Regards,
Bo Shen

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[U-Boot] [PATCH 2/2] ARMv7: at91: enable ICache and DCache.

2014-05-16 Thread Josh Wu 
As SAMA5D3 is a at91 ARMv7 cpu, so we should enable LCD DCache
flush for SAMA5D3X-EK.

Signed-off-by: Josh Wu 
---
 arch/arm/cpu/armv7/at91/cpu.c   |6 ++
 board/atmel/sama5d3xek/sama5d3xek.c |6 +-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/at91/cpu.c b/arch/arm/cpu/armv7/at91/cpu.c
index 2fbf60d..6f2164f 100644
--- a/arch/arm/cpu/armv7/at91/cpu.c
+++ b/arch/arm/cpu/armv7/at91/cpu.c
@@ -61,6 +61,12 @@ int print_cpuinfo(void)
 
 void enable_caches(void)
 {
+#ifndef CONFIG_SYS_ICACHE_OFF
+   icache_enable();
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+   dcache_enable();
+#endif
 }
 
 unsigned int get_chip_id(void)
diff --git a/board/atmel/sama5d3xek/sama5d3xek.c 
b/board/atmel/sama5d3xek/sama5d3xek.c
index c835c12..1fc91d9 100644
--- a/board/atmel/sama5d3xek/sama5d3xek.c
+++ b/board/atmel/sama5d3xek/sama5d3xek.c
@@ -200,8 +200,12 @@ int board_init(void)
at91_gmac_hw_init();
 #endif
 #ifdef CONFIG_LCD
-   if (has_lcdc())
+   if (has_lcdc()) {
sama5d3xek_lcd_hw_init();
+
+   /* Enable flushing as we enabled dcache */
+   lcd_set_flush_dcache(1);
+   }
 #endif
return 0;
 }
-- 
1.7.9.5

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