Re: [U-Boot] [PATCH 2/2] MIPS: Coding style cleanups on common assembly files
On 04/12/2011 12:35 AM, Daniel Schwierzeck wrote: diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S index 0a9d9d5..f1e3447 100644 --- a/arch/mips/cpu/mips32/start.S +++ b/arch/mips/cpu/mips32/start.S @@ -62,11 +62,11 @@ .globl _start .text _start: - RVECENT(reset,0)/* U-boot entry point */ - RVECENT(reset,1)/* software reboot */ -#if defined(CONFIG_INCA_IP) - .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */ - .word 0x /* phase of the flash */ + RVECENT(reset,0)# U-boot entry point + RVECENT(reset,1)# software reboot +#ifdef CONFIG_INCA_IP + .word INFINEON_EBU_BOOTCFG # EBU init code, fetched during + .word 0x# booting phase of the flash #else RVECENT(romReserved,2) #endif can we use #ifdef INFINEON_EBU_BOOTCFG instead? This would help me with other SOCs which uses this feature too. I don't see any problem with that plan, although I'm not sure what EBU stands for and whether it could be generalized for other SoCs or not at this moment. Anyway patches are welcome. But that's out of the scope of this clean- up patch, so should be prepared separately. you missed that line: XVECENT(romExcHandle,0x380) /* bfc00380: R4000 general vector */ Thanks, now fixed. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] MIPS: Coding style cleanups on common assembly files
Hi Shinya, I have some minor additions 2011/4/9 Shinya Kuribayashi skuri...@pobox.com: Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi skuri...@pobox.com --- arch/mips/cpu/mips32/cache.S | 81 ++--- arch/mips/cpu/mips32/start.S | 117 +++-- 2 files changed, 92 insertions(+), 106 deletions(-) diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S [...] diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S index 0a9d9d5..f1e3447 100644 --- a/arch/mips/cpu/mips32/start.S +++ b/arch/mips/cpu/mips32/start.S @@ -62,11 +62,11 @@ .globl _start .text _start: - RVECENT(reset,0) /* U-boot entry point */ - RVECENT(reset,1) /* software reboot */ -#if defined(CONFIG_INCA_IP) - .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */ - .word 0x /* phase of the flash */ + RVECENT(reset,0) # U-boot entry point + RVECENT(reset,1) # software reboot +#ifdef CONFIG_INCA_IP + .word INFINEON_EBU_BOOTCFG # EBU init code, fetched during + .word 0x # booting phase of the flash #else RVECENT(romReserved,2) #endif can we use #ifdef INFINEON_EBU_BOOTCFG instead? This would help me with other SOCs which uses this feature too. @@ -131,7 +131,7 @@ _start: RVECENT(romReserved,61) RVECENT(romReserved,62) RVECENT(romReserved,63) - XVECENT(romExcHandle,0x200) /* bfc00200: R4000 tlbmiss vector */ + XVECENT(romExcHandle,0x200) # bfc00200: R4000 tlbmiss vector RVECENT(romReserved,65) RVECENT(romReserved,66) RVECENT(romReserved,67) @@ -147,7 +147,7 @@ _start: RVECENT(romReserved,77) RVECENT(romReserved,78) RVECENT(romReserved,79) - XVECENT(romExcHandle,0x280) /* bfc00280: R4000 xtlbmiss vector */ + XVECENT(romExcHandle,0x280) # bfc00280: R4000 xtlbmiss vector RVECENT(romReserved,81) RVECENT(romReserved,82) RVECENT(romReserved,83) @@ -163,7 +163,7 @@ _start: RVECENT(romReserved,93) RVECENT(romReserved,94) RVECENT(romReserved,95) - XVECENT(romExcHandle,0x300) /* bfc00300: R4000 cache vector */ + XVECENT(romExcHandle,0x300) # bfc00300: R4000 cache vector RVECENT(romReserved,97) RVECENT(romReserved,98) RVECENT(romReserved,99) you missed that line: XVECENT(romExcHandle,0x380) /* bfc00380: R4000 general vector */ @@ -196,19 +196,19 @@ _start: RVECENT(romReserved,126) RVECENT(romReserved,127) - /* We hope there are no more reserved vectors! + /* + * We hope there are no more reserved vectors! * 128 * 8 == 1024 == 0x400 * so this is address R_VEC+0x400 == 0xbfc00400 */ .align 4 reset: - /* Clear watch registers. - */ + /* Clear watch registers */ mtc0 zero, CP0_WATCHLO mtc0 zero, CP0_WATCHHI [...] Best regards Daniel ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] MIPS: Coding style cleanups on common assembly files
Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi skuri...@pobox.com --- arch/mips/cpu/mips32/cache.S | 81 ++--- arch/mips/cpu/mips32/start.S | 117 +++-- 2 files changed, 92 insertions(+), 106 deletions(-) diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S index edc0674..5ce0ec4 100644 --- a/arch/mips/cpu/mips32/cache.S +++ b/arch/mips/cpu/mips32/cache.S @@ -76,8 +76,8 @@ * mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz) */ LEAF(mips_init_icache) - bleza1, 9f - mtc0zero, CP0_TAGLO + bleza1, 9f + mtc0zero, CP0_TAGLO /* clear tag to invalidate */ PTR_LI t0, INDEX_BASE PTR_ADDUt1, t0, a1 @@ -94,15 +94,15 @@ LEAF(mips_init_icache) 1: cache_opIndex_Store_Tag_I t0 PTR_ADDUt0, a2 bne t0, t1, 1b -9: jr ra +9: jr ra END(mips_init_icache) /* * mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz) */ LEAF(mips_init_dcache) - bleza1, 9f - mtc0zero, CP0_TAGLO + bleza1, 9f + mtc0zero, CP0_TAGLO /* clear all tags */ PTR_LI t0, INDEX_BASE PTR_ADDUt1, t0, a1 @@ -119,25 +119,23 @@ LEAF(mips_init_dcache) 1: cache_opIndex_Store_Tag_D t0 PTR_ADDUt0, a2 bne t0, t1, 1b -9: jr ra +9: jr ra END(mips_init_dcache) -/*** -* -* mips_cache_reset - low level initialisation of the primary caches -* -* This routine initialises the primary caches to ensure that they -* have good parity. It must be called by the ROM before any cached locations -* are used to prevent the possibility of data with bad parity being written to -* memory. -* To initialise the instruction cache it is essential that a source of data -* with good parity is available. This routine -* will initialise an area of memory starting at location zero to be used as -* a source of parity. -* -* RETURNS: N/A -* -*/ +/* + * mips_cache_reset - low level initialisation of the primary caches + * + * This routine initialises the primary caches to ensure that they have good + * parity. It must be called by the ROM before any cached locations are used + * to prevent the possibility of data with bad parity being written to memory. + * + * To initialise the instruction cache it is essential that a source of data + * with good parity is available. This routine will initialise an area of + * memory starting at location zero to be used as a source of parity. + * + * RETURNS: N/A + * + */ NESTED(mips_cache_reset, 0, ra) moveRA, ra li t2, CONFIG_SYS_ICACHE_SIZE @@ -185,13 +183,12 @@ NESTED(mips_cache_reset, 0, ra) jr RA END(mips_cache_reset) -/*** -* -* dcache_status - get cache status -* -* RETURNS: 0 - cache disabled; 1 - cache enabled -* -*/ +/* + * dcache_status - get cache status + * + * RETURNS: 0 - cache disabled; 1 - cache enabled + * + */ LEAF(dcache_status) mfc0t0, CP0_CONFIG li t1, CONF_CM_UNCACHED @@ -202,13 +199,12 @@ LEAF(dcache_status) 2: jr ra END(dcache_status) -/*** -* -* dcache_disable - disable cache -* -* RETURNS: N/A -* -*/ +/* + * dcache_disable - disable cache + * + * RETURNS: N/A + * + */ LEAF(dcache_disable) mfc0t0, CP0_CONFIG li t1, -8 @@ -218,13 +214,12 @@ LEAF(dcache_disable) jr ra END(dcache_disable) -/*** -* -* dcache_enable - enable cache -* -* RETURNS: N/A -* -*/ +/* + * dcache_enable - enable cache + * + * RETURNS: N/A + * + */ LEAF(dcache_enable) mfc0t0, CP0_CONFIG ori t0, CONF_CM_CMASK diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S index 0a9d9d5..f1e3447 100644 --- a/arch/mips/cpu/mips32/start.S +++ b/arch/mips/cpu/mips32/start.S @@ -62,11 +62,11 @@ .globl _start .text _start: - RVECENT(reset,0)/* U-boot entry point */ - RVECENT(reset,1)/* software reboot */ -#if defined(CONFIG_INCA_IP) - .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */ - .word 0x /* phase of the flash*/ +
