Re: [U-Boot] [PATCH 2/2] net: phy: micrel: fix divisor value for KSZ9031 phy skew
On 01/27/2016 07:26 PM, Måns Rullgård wrote: > writes: > >> From: Dinh Nguyen >> >> The picoseconds to register value divisor(ps_to_regval) should be 60 and not >> 200. Linux has KSZ9031_PS_TO_REG defined to be 60 as well. 60 is the correct >> divisor because the 4-bit skew values are defined from 0x(-420ps) to >> 0x(480ps), increments of 60. >> >> For example, a DTS skew value of 420, represents 0ps delay, which should be >> 0x7. >> With the previous divisor of 200, it would result in 0x2, which represents a >> -300ps delay. >> >> With this patch, ethernet on the SoCFPGA DE0 Atlas is now able to work with >> 1Gb ethernet. > > Is this expected to make any difference on the Altera socdk? Both with > and without the patch, it takes a very long time (sometimes minutes) to > negotiate a link, but once it does it works fine. > The Altera socdk uses a different PHY, KSZ9021, so no, this patch will not affect that hardware. I'll check out your link issues on the socdk when I get a chance. Dinh ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] net: phy: micrel: fix divisor value for KSZ9031 phy skew
writes:
> From: Dinh Nguyen
>
> The picoseconds to register value divisor(ps_to_regval) should be 60 and not
> 200. Linux has KSZ9031_PS_TO_REG defined to be 60 as well. 60 is the correct
> divisor because the 4-bit skew values are defined from 0x(-420ps) to
> 0x(480ps), increments of 60.
>
> For example, a DTS skew value of 420, represents 0ps delay, which should be
> 0x7.
> With the previous divisor of 200, it would result in 0x2, which represents a
> -300ps delay.
>
> With this patch, ethernet on the SoCFPGA DE0 Atlas is now able to work with
> 1Gb ethernet.
Is this expected to make any difference on the Altera socdk? Both with
and without the patch, it takes a very long time (sometimes minutes) to
negotiate a link, but once it does it works fine.
> References:
> http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf -> page 26
>
> Signed-off-by: Dinh Nguyen
> ---
> drivers/net/phy/micrel.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
> index 19b6bc7..2530a5b 100644
> --- a/drivers/net/phy/micrel.c
> +++ b/drivers/net/phy/micrel.c
> @@ -211,7 +211,7 @@ static int ksz90x1_of_config_group(struct phy_device
> *phydev,
> {
> struct udevice *dev = phydev->dev;
> struct phy_driver *drv = phydev->drv;
> - const int ps_to_regval = 200;
> + const int ps_to_regval = 60;
> int val[4];
> int i, changed = 0, offset, max;
> u16 regval = 0;
> --
> 2.6.2
--
Måns Rullgård
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Re: [U-Boot] [PATCH 2/2] net: phy: micrel: fix divisor value for KSZ9031 phy skew
On Wednesday, January 27, 2016 at 11:53:29 PM, Joe Hershberger wrote: > Hi Marek, > > On Wed, Jan 27, 2016 at 4:07 PM, Marek Vasut wrote: > > On Wednesday, January 27, 2016 at 10:46:00 PM, > > dingu...@opensource.altera.com > > > > wrote: > >> From: Dinh Nguyen > >> > >> The picoseconds to register value divisor(ps_to_regval) should be 60 and > >> not 200. Linux has KSZ9031_PS_TO_REG defined to be 60 as well. 60 is the > >> correct divisor because the 4-bit skew values are defined from > >> 0x(-420ps) to 0x(480ps), increments of 60. > >> > >> For example, a DTS skew value of 420, represents 0ps delay, which should > >> be 0x7. With the previous divisor of 200, it would result in 0x2, which > >> represents a -300ps delay. > >> > >> With this patch, ethernet on the SoCFPGA DE0 Atlas is now able to work > >> with 1Gb ethernet. > >> > >> References: > >> http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf -> page 26 > >> > >> Signed-off-by: Dinh Nguyen > > > > This is fine, thanks for spotting it. > > > > Acked-by: Marek Vasut > > > > Joe, will you pick these two and push for 2016.03 or shall I pick them ? > > I'll get them. Roger, thanks! Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] net: phy: micrel: fix divisor value for KSZ9031 phy skew
On Wed, Jan 27, 2016 at 3:46 PM, wrote: > From: Dinh Nguyen > > The picoseconds to register value divisor(ps_to_regval) should be 60 and not > 200. Linux has KSZ9031_PS_TO_REG defined to be 60 as well. 60 is the correct > divisor because the 4-bit skew values are defined from 0x(-420ps) to > 0x(480ps), increments of 60. > > For example, a DTS skew value of 420, represents 0ps delay, which should be > 0x7. > With the previous divisor of 200, it would result in 0x2, which represents a > -300ps delay. > > With this patch, ethernet on the SoCFPGA DE0 Atlas is now able to work with > 1Gb ethernet. > > References: > http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf -> page 26 > > Signed-off-by: Dinh Nguyen Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] net: phy: micrel: fix divisor value for KSZ9031 phy skew
Hi Marek, On Wed, Jan 27, 2016 at 4:07 PM, Marek Vasut wrote: > On Wednesday, January 27, 2016 at 10:46:00 PM, dingu...@opensource.altera.com > wrote: >> From: Dinh Nguyen >> >> The picoseconds to register value divisor(ps_to_regval) should be 60 and >> not 200. Linux has KSZ9031_PS_TO_REG defined to be 60 as well. 60 is the >> correct divisor because the 4-bit skew values are defined from >> 0x(-420ps) to 0x(480ps), increments of 60. >> >> For example, a DTS skew value of 420, represents 0ps delay, which should be >> 0x7. With the previous divisor of 200, it would result in 0x2, which >> represents a -300ps delay. >> >> With this patch, ethernet on the SoCFPGA DE0 Atlas is now able to work with >> 1Gb ethernet. >> >> References: >> http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf -> page 26 >> >> Signed-off-by: Dinh Nguyen > > This is fine, thanks for spotting it. > > Acked-by: Marek Vasut > > Joe, will you pick these two and push for 2016.03 or shall I pick them ? I'll get them. -Joe ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] net: phy: micrel: fix divisor value for KSZ9031 phy skew
On Wednesday, January 27, 2016 at 10:46:00 PM, dingu...@opensource.altera.com wrote: > From: Dinh Nguyen > > The picoseconds to register value divisor(ps_to_regval) should be 60 and > not 200. Linux has KSZ9031_PS_TO_REG defined to be 60 as well. 60 is the > correct divisor because the 4-bit skew values are defined from > 0x(-420ps) to 0x(480ps), increments of 60. > > For example, a DTS skew value of 420, represents 0ps delay, which should be > 0x7. With the previous divisor of 200, it would result in 0x2, which > represents a -300ps delay. > > With this patch, ethernet on the SoCFPGA DE0 Atlas is now able to work with > 1Gb ethernet. > > References: > http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf -> page 26 > > Signed-off-by: Dinh Nguyen This is fine, thanks for spotting it. Acked-by: Marek Vasut Joe, will you pick these two and push for 2016.03 or shall I pick them ? Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] net: phy: micrel: fix divisor value for KSZ9031 phy skew
From: Dinh Nguyen
The picoseconds to register value divisor(ps_to_regval) should be 60 and not
200. Linux has KSZ9031_PS_TO_REG defined to be 60 as well. 60 is the correct
divisor because the 4-bit skew values are defined from 0x(-420ps) to
0x(480ps), increments of 60.
For example, a DTS skew value of 420, represents 0ps delay, which should be 0x7.
With the previous divisor of 200, it would result in 0x2, which represents a
-300ps delay.
With this patch, ethernet on the SoCFPGA DE0 Atlas is now able to work with
1Gb ethernet.
References:
http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf -> page 26
Signed-off-by: Dinh Nguyen
---
drivers/net/phy/micrel.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index 19b6bc7..2530a5b 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -211,7 +211,7 @@ static int ksz90x1_of_config_group(struct phy_device
*phydev,
{
struct udevice *dev = phydev->dev;
struct phy_driver *drv = phydev->drv;
- const int ps_to_regval = 200;
+ const int ps_to_regval = 60;
int val[4];
int i, changed = 0, offset, max;
u16 regval = 0;
--
2.6.2
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