Re: [U-Boot] [PATCH 2/2] pinctrl: rockchip: Add pinctrl support for rk3308

2019-11-26 Thread Kever Yang 

David,


On 2019/11/26 上午9:06, David Wu wrote:

The most pins of rk3308 are 2bits iomux, but the banks's register
width is 0x8.


Could you make more explanation about the difference for rk3308 iomux? 
It will be better


to have a simple example here.


Thanks,

- Kever



Signed-off-by: David Wu 
---
  drivers/pinctrl/rockchip/Makefile |   1 +
  drivers/pinctrl/rockchip/pinctrl-rk3308.c | 464 ++
  .../pinctrl/rockchip/pinctrl-rockchip-core.c  |   3 +-
  drivers/pinctrl/rockchip/pinctrl-rockchip.h   |   1 +
  4 files changed, 468 insertions(+), 1 deletion(-)
  create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3308.c

diff --git a/drivers/pinctrl/rockchip/Makefile 
b/drivers/pinctrl/rockchip/Makefile
index 83913f668f..fcf19f877a 100644
--- a/drivers/pinctrl/rockchip/Makefile
+++ b/drivers/pinctrl/rockchip/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_ROCKCHIP_RK3128) += pinctrl-rk3128.o
  obj-$(CONFIG_ROCKCHIP_RK3188) += pinctrl-rk3188.o
  obj-$(CONFIG_ROCKCHIP_RK322X) += pinctrl-rk322x.o
  obj-$(CONFIG_ROCKCHIP_RK3288) += pinctrl-rk3288.o
+obj-$(CONFIG_ROCKCHIP_RK3308) += pinctrl-rk3308.o
  obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o
  obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o
  obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o
diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3308.c 
b/drivers/pinctrl/rockchip/pinctrl-rk3308.c
new file mode 100644
index 00..abd57e54a5
--- /dev/null
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3308.c
@@ -0,0 +1,464 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "pinctrl-rockchip.h"
+
+static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
+   {
+   .num = 1,
+   .pin = 14,
+   .reg = 0x28,
+   .bit = 12,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 15,
+   .reg = 0x2c,
+   .bit = 0,
+   .mask = 0x3
+   }, {
+   .num = 1,
+   .pin = 18,
+   .reg = 0x30,
+   .bit = 4,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 19,
+   .reg = 0x30,
+   .bit = 8,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 20,
+   .reg = 0x30,
+   .bit = 12,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 21,
+   .reg = 0x34,
+   .bit = 0,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 22,
+   .reg = 0x34,
+   .bit = 4,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 23,
+   .reg = 0x34,
+   .bit = 8,
+   .mask = 0xf
+   }, {
+   .num = 3,
+   .pin = 12,
+   .reg = 0x68,
+   .bit = 8,
+   .mask = 0xf
+   }, {
+   .num = 3,
+   .pin = 13,
+   .reg = 0x68,
+   .bit = 12,
+   .mask = 0xf
+   }, {
+   .num = 2,
+   .pin = 2,
+   .reg = 0x608,
+   .bit = 0,
+   .mask = 0x7
+   }, {
+   .num = 2,
+   .pin = 3,
+   .reg = 0x608,
+   .bit = 4,
+   .mask = 0x7
+   }, {
+   .num = 2,
+   .pin = 16,
+   .reg = 0x610,
+   .bit = 8,
+   .mask = 0x7
+   }, {
+   .num = 3,
+   .pin = 10,
+   .reg = 0x610,
+   .bit = 0,
+   .mask = 0x7
+   }, {
+   .num = 3,
+   .pin = 11,
+   .reg = 0x610,
+   .bit = 4,
+   .mask = 0x7
+   },
+};
+
+static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
+   {
+   /* rtc_clk */
+   .bank_num = 0,
+   .pin = 19,
+   .func = 1,
+   .route_offset = 0x314,
+   .route_val = BIT(16 + 0) | BIT(0),
+   }, {
+   /* uart2_rxm0 */
+   .bank_num = 1,
+   .pin = 22,
+   .func = 2,
+   .route_offset = 0x314,
+   .route_val = BIT(16 + 2) | BIT(16 + 3),
+   }, {
+   /* uart2_rxm1 */
+   .bank_num = 4,
+   .pin = 26,
+   .func = 2,
+   .route_offset = 0x314,
+   .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2),
+   }, {
+   /* i2c3_sdam0 */
+   .bank_num = 0,
+   .pin = 15,
+   .func = 2,
+   .route_offset = 0x608,
+   .route_val = BIT(16 + 8) |

[U-Boot] [PATCH 2/2] pinctrl: rockchip: Add pinctrl support for rk3308

2019-11-25 Thread David Wu 
The most pins of rk3308 are 2bits iomux, but the banks's register
width is 0x8.

Signed-off-by: David Wu 
---
 drivers/pinctrl/rockchip/Makefile |   1 +
 drivers/pinctrl/rockchip/pinctrl-rk3308.c | 464 ++
 .../pinctrl/rockchip/pinctrl-rockchip-core.c  |   3 +-
 drivers/pinctrl/rockchip/pinctrl-rockchip.h   |   1 +
 4 files changed, 468 insertions(+), 1 deletion(-)
 create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3308.c

diff --git a/drivers/pinctrl/rockchip/Makefile 
b/drivers/pinctrl/rockchip/Makefile
index 83913f668f..fcf19f877a 100644
--- a/drivers/pinctrl/rockchip/Makefile
+++ b/drivers/pinctrl/rockchip/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_ROCKCHIP_RK3128) += pinctrl-rk3128.o
 obj-$(CONFIG_ROCKCHIP_RK3188) += pinctrl-rk3188.o
 obj-$(CONFIG_ROCKCHIP_RK322X) += pinctrl-rk322x.o
 obj-$(CONFIG_ROCKCHIP_RK3288) += pinctrl-rk3288.o
+obj-$(CONFIG_ROCKCHIP_RK3308) += pinctrl-rk3308.o
 obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o
 obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o
 obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o
diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3308.c 
b/drivers/pinctrl/rockchip/pinctrl-rk3308.c
new file mode 100644
index 00..abd57e54a5
--- /dev/null
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3308.c
@@ -0,0 +1,464 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "pinctrl-rockchip.h"
+
+static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
+   {
+   .num = 1,
+   .pin = 14,
+   .reg = 0x28,
+   .bit = 12,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 15,
+   .reg = 0x2c,
+   .bit = 0,
+   .mask = 0x3
+   }, {
+   .num = 1,
+   .pin = 18,
+   .reg = 0x30,
+   .bit = 4,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 19,
+   .reg = 0x30,
+   .bit = 8,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 20,
+   .reg = 0x30,
+   .bit = 12,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 21,
+   .reg = 0x34,
+   .bit = 0,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 22,
+   .reg = 0x34,
+   .bit = 4,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 23,
+   .reg = 0x34,
+   .bit = 8,
+   .mask = 0xf
+   }, {
+   .num = 3,
+   .pin = 12,
+   .reg = 0x68,
+   .bit = 8,
+   .mask = 0xf
+   }, {
+   .num = 3,
+   .pin = 13,
+   .reg = 0x68,
+   .bit = 12,
+   .mask = 0xf
+   }, {
+   .num = 2,
+   .pin = 2,
+   .reg = 0x608,
+   .bit = 0,
+   .mask = 0x7
+   }, {
+   .num = 2,
+   .pin = 3,
+   .reg = 0x608,
+   .bit = 4,
+   .mask = 0x7
+   }, {
+   .num = 2,
+   .pin = 16,
+   .reg = 0x610,
+   .bit = 8,
+   .mask = 0x7
+   }, {
+   .num = 3,
+   .pin = 10,
+   .reg = 0x610,
+   .bit = 0,
+   .mask = 0x7
+   }, {
+   .num = 3,
+   .pin = 11,
+   .reg = 0x610,
+   .bit = 4,
+   .mask = 0x7
+   },
+};
+
+static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
+   {
+   /* rtc_clk */
+   .bank_num = 0,
+   .pin = 19,
+   .func = 1,
+   .route_offset = 0x314,
+   .route_val = BIT(16 + 0) | BIT(0),
+   }, {
+   /* uart2_rxm0 */
+   .bank_num = 1,
+   .pin = 22,
+   .func = 2,
+   .route_offset = 0x314,
+   .route_val = BIT(16 + 2) | BIT(16 + 3),
+   }, {
+   /* uart2_rxm1 */
+   .bank_num = 4,
+   .pin = 26,
+   .func = 2,
+   .route_offset = 0x314,
+   .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2),
+   }, {
+   /* i2c3_sdam0 */
+   .bank_num = 0,
+   .pin = 15,
+   .func = 2,
+   .route_offset = 0x608,
+   .route_val = BIT(16 + 8) | BIT(16 + 9),
+   }, {
+   /* i2c3_sdam1 */
+   .bank_num = 3,
+   .pin = 12,
+   .func = 2,
+   .route_offset = 0x608,
+