From: Jason Jin jason@freescale.com
T1042 has internal display interface unit (DIU) for driving video.
T1042RDB supports video mode via
-LCD using TI enconder
-HDMI type interface via HDMI encoder
Chrontel, CH7301C encoder which is I2C programmable is used
as HDMI connector on T1042RDB.
This patch add support to
-enable Video interface for T1042RDB
-route qixis multiplexing to enable DIU-HDMI interface on board
-program DIU pixel clock gerenartor for T1042
-program HDMI encoder via I2C on board
This patch refer to the upstream diu patch
(337b0c52b3296f371d04aef71a833e09110e0e6b) for T1040qds.
Signed-off-by: Jason Jin jason@freescale.com
Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
This patch depends on CPLD.
Ozlab link: http://patchwork.ozlabs.org/patch/328180/
diff --git a/board/freescale/t104xrdb/Makefile
b/board/freescale/t104xrdb/Makefile
index af38d9f..f15a633 100644
--- a/board/freescale/t104xrdb/Makefile
+++ b/board/freescale/t104xrdb/Makefile
@@ -12,3 +12,4 @@ obj-$(CONFIG_PCI) += pci.o
obj-y += law.o
obj-y += tlb.o
obj-y += cpld.o
+obj-$(CONFIG_FSL_DIU_FB) += diu.o
diff --git a/board/freescale/t104xrdb/diu.c b/board/freescale/t104xrdb/diu.c
new file mode 100644
index 000..a4f378c
--- /dev/null
+++ b/board/freescale/t104xrdb/diu.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Author: Priyanka Jain priyanka.j...@freescale.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include asm/io.h
+#include common.h
+#include command.h
+#include fsl_diu_fb.h
+#include linux/ctype.h
+#include video_fb.h
+
+#include ../common/diu_ch7301.h
+
+#include cpld.h
+#include t104xrdb.h
+
+/*
+ * DIU Area Descriptor
+ *
+ * Note that we need to byte-swap the value before it's written to the AD
+ * register. So even though the registers don't look like they're in the same
+ * bit positions as they are on the MPC8610, the same value is written to the
+ * AD register on the MPC8610 and on the P1022.
+ */
+#define AD_BYTE_F 0x1000
+#define AD_ALPHA_C_SHIFT 25
+#define AD_BLUE_C_SHIFT23
+#define AD_GREEN_C_SHIFT 21
+#define AD_RED_C_SHIFT 19
+#define AD_PIXEL_S_SHIFT 16
+#define AD_COMP_3_SHIFT12
+#define AD_COMP_2_SHIFT8
+#define AD_COMP_1_SHIFT4
+#define AD_COMP_0_SHIFT0
+
+void diu_set_pixel_clock(unsigned int pixclock)
+{
+ unsigned long speed_ccb, temp;
+ u32 pixval;
+ int ret;
+ speed_ccb = get_bus_freq(0);
+ temp = 10 / pixclock;
+ temp *= 1000;
+ pixval = speed_ccb / temp;
+
+ /* Program HDMI encoder */
+ ret = diu_set_dvi_encoder(temp);
+ if (ret) {
+ puts(Failed to set DVI encoder\n);
+ return;
+ }
+
+ /* Program pixel clock */
+ out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR,
+((pixval PXCK_BITS_START) PXCK_MASK));
+ /* enable clock*/
+ out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK |
+((pixval PXCK_BITS_START) PXCK_MASK));
+}
+
+int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
+{
+ u32 pixel_format;
+ u8 sw;
+
+ /*Configure Display ouput port as HDMI*/
+ sw = CPLD_READ(sfp_ctl_status);
+ CPLD_WRITE(sfp_ctl_status , sw ~(CPLD_DIU_SEL_DFP));
+
+ pixel_format = cpu_to_le32(AD_BYTE_F | (3 AD_ALPHA_C_SHIFT) |
+ (0 AD_BLUE_C_SHIFT) | (1 AD_GREEN_C_SHIFT) |
+ (2 AD_RED_C_SHIFT) | (8 AD_COMP_3_SHIFT) |
+ (8 AD_COMP_2_SHIFT) | (8 AD_COMP_1_SHIFT) |
+ (8 AD_COMP_0_SHIFT) | (3 AD_PIXEL_S_SHIFT));
+
+ printf(DIU: Switching to monitor DVI @ %ux%u\n, xres, yres);
+
+ return fsl_diu_init(xres, yres, pixel_format, 0);
+}
diff --git a/include/configs/T1042RDB_PI.h b/include/configs/T1042RDB_PI.h
index 8a8a2ff..0d0f1cd 100644
--- a/include/configs/T1042RDB_PI.h
+++ b/include/configs/T1042RDB_PI.h
@@ -203,6 +203,7 @@
#define CPLD_LBMAP_DFLTBANK0x40 /* BANK OR | BANK0 */
#define CPLD_LBMAP_RESET 0xFF
#define CPLD_LBMAP_SHIFT 0x03
+#define CPLD_DIU_SEL_DFP 0x80
#define CONFIG_SYS_CPLD_BASE 0xffdf
#define CONFIG_SYS_CPLD_BASE_PHYS (0xfull | CONFIG_SYS_CPLD_BASE)
@@ -332,7 +333,8 @@
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
+/*When DIU is enabled, more malloc memory needed for fb*/
+#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
/* Serial Port - controlled on board with jumper J8
* open - index 2
@@ -352,12 +354,27 @@
#define CONFIG_SYS_NS16550_COM3(CONFIG_SYS_CCSRBAR+0x11D500)
#define CONFIG_SYS_NS16550_COM4(CONFIG_SYS_CCSRBAR+0x11D600)
#define
