Re: [U-Boot] [PATCH 2/2] riscv: dts: Add ae350_32.dts for 32 bit
Hi Rick,
On Thu, Oct 25, 2018 at 4:23 PM Rick Chen wrote:
>
> Rick Chen 於 2018年10月16日 週二 上午10:01寫道：
> >
> > Bin Meng 於 2018年10月8日 週一 下午11:48寫道：
> > >
> > > Hi Rick,
> > >
> > > On Mon, Oct 8, 2018 at 1:37 PM Andes wrote:
> > > >
> > > > From: Rick Chen
> > > >
> > > > Add ae350_32.dts for 32 bit. And also rename
> > > > ae350.dts to ae350_64.dts for 64 bit.
> > > >
> > > > Signed-off-by: Rick Chen
> > > > Cc: Greentime Hu
> > > > ---
> > > > arch/riscv/dts/ae350.dts| 229
> > > >
> > > > arch/riscv/dts/ae350_32.dts | 229
> > > >
> > > > arch/riscv/dts/ae350_64.dts | 229
> > > >
> > > > 3 files changed, 458 insertions(+), 229 deletions(-)
> > > > delete mode 100644 arch/riscv/dts/ae350.dts
> > > > create mode 100644 arch/riscv/dts/ae350_32.dts
> > > > create mode 100644 arch/riscv/dts/ae350_64.dts
> > > >
> > >
> > > It looks to me that the only difference between these two dts files
> > > are the cpu node (rv32 vs rv64). Can we please put the common part
> > > into a dtsi file and let the main dts file include the dtsi file and
> > > override anything if needed?
> > >
> >
> > Hi Bin
> >
> > I will separate the common into a dtsi file. And others into dts file.
> >
>
> Hi Bin
>
> I am trying to put the common part in a ae350.dtsi from ae350_32.dts
> and ae350_64.dts.
> But i encounter a problem as below :
>
> smc node for 32 bit :
>
> smc0: smc@e040 {
> compatible = "andestech,atfsmc020";
> reg = <0xe040 0x1000>;
> };
>
> smc node for 64 bit :
>
> smc0: smc@e040 {
> compatible = "andestech,atfsmc020";
> reg = <0x0 0xe040 0x0 0x1000>;
> };
>
> Though they look like almost the same, but their reg is different.
> Since can not put in a dtsi file for sharing.
>
> Do you have any idea ?
>
So the register physical address and size are the same and both are
below 4GB. In such case, the 64-bit DTS should have the same
#address-cells and #size-cells as the 32-bit one.
Regards,
Bin
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Re: [U-Boot] [PATCH 2/2] riscv: dts: Add ae350_32.dts for 32 bit
Rick Chen 於 2018年10月16日 週二 上午10:01寫道：
>
> Bin Meng 於 2018年10月8日 週一 下午11:48寫道：
> >
> > Hi Rick,
> >
> > On Mon, Oct 8, 2018 at 1:37 PM Andes wrote:
> > >
> > > From: Rick Chen
> > >
> > > Add ae350_32.dts for 32 bit. And also rename
> > > ae350.dts to ae350_64.dts for 64 bit.
> > >
> > > Signed-off-by: Rick Chen
> > > Cc: Greentime Hu
> > > ---
> > > arch/riscv/dts/ae350.dts| 229
> > >
> > > arch/riscv/dts/ae350_32.dts | 229
> > >
> > > arch/riscv/dts/ae350_64.dts | 229
> > >
> > > 3 files changed, 458 insertions(+), 229 deletions(-)
> > > delete mode 100644 arch/riscv/dts/ae350.dts
> > > create mode 100644 arch/riscv/dts/ae350_32.dts
> > > create mode 100644 arch/riscv/dts/ae350_64.dts
> > >
> >
> > It looks to me that the only difference between these two dts files
> > are the cpu node (rv32 vs rv64). Can we please put the common part
> > into a dtsi file and let the main dts file include the dtsi file and
> > override anything if needed?
> >
>
> Hi Bin
>
> I will separate the common into a dtsi file. And others into dts file.
>
Hi Bin
I am trying to put the common part in a ae350.dtsi from ae350_32.dts
and ae350_64.dts.
But i encounter a problem as below :
smc node for 32 bit :
smc0: smc@e040 {
compatible = "andestech,atfsmc020";
reg = <0xe040 0x1000>;
};
smc node for 64 bit :
smc0: smc@e040 {
compatible = "andestech,atfsmc020";
reg = <0x0 0xe040 0x0 0x1000>;
};
Though they look like almost the same, but their reg is different.
Since can not put in a dtsi file for sharing.
Do you have any idea ?
Rick
> Thanks
>
> Rick
>
> > Regards,
> > Bin
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Re: [U-Boot] [PATCH 2/2] riscv: dts: Add ae350_32.dts for 32 bit
Bin Meng 於 2018年10月8日 週一 下午11:48寫道： > > Hi Rick, > > On Mon, Oct 8, 2018 at 1:37 PM Andes wrote: > > > > From: Rick Chen > > > > Add ae350_32.dts for 32 bit. And also rename > > ae350.dts to ae350_64.dts for 64 bit. > > > > Signed-off-by: Rick Chen > > Cc: Greentime Hu > > --- > > arch/riscv/dts/ae350.dts| 229 > > > > arch/riscv/dts/ae350_32.dts | 229 > > > > arch/riscv/dts/ae350_64.dts | 229 > > > > 3 files changed, 458 insertions(+), 229 deletions(-) > > delete mode 100644 arch/riscv/dts/ae350.dts > > create mode 100644 arch/riscv/dts/ae350_32.dts > > create mode 100644 arch/riscv/dts/ae350_64.dts > > > > It looks to me that the only difference between these two dts files > are the cpu node (rv32 vs rv64). Can we please put the common part > into a dtsi file and let the main dts file include the dtsi file and > override anything if needed? > Hi Bin I will separate the common into a dtsi file. And others into dts file. Thanks Rick > Regards, > Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] riscv: dts: Add ae350_32.dts for 32 bit
Hi Rick, On Mon, Oct 8, 2018 at 1:37 PM Andes wrote: > > From: Rick Chen > > Add ae350_32.dts for 32 bit. And also rename > ae350.dts to ae350_64.dts for 64 bit. > > Signed-off-by: Rick Chen > Cc: Greentime Hu > --- > arch/riscv/dts/ae350.dts| 229 > > arch/riscv/dts/ae350_32.dts | 229 > > arch/riscv/dts/ae350_64.dts | 229 > > 3 files changed, 458 insertions(+), 229 deletions(-) > delete mode 100644 arch/riscv/dts/ae350.dts > create mode 100644 arch/riscv/dts/ae350_32.dts > create mode 100644 arch/riscv/dts/ae350_64.dts > It looks to me that the only difference between these two dts files are the cpu node (rv32 vs rv64). Can we please put the common part into a dtsi file and let the main dts file include the dtsi file and override anything if needed? Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 2/2] riscv: dts: Add ae350_32.dts for 32 bit
From: Rick Chen
Add ae350_32.dts for 32 bit. And also rename
ae350.dts to ae350_64.dts for 64 bit.
Signed-off-by: Rick Chen
Cc: Greentime Hu
---
arch/riscv/dts/ae350.dts| 229
arch/riscv/dts/ae350_32.dts | 229
arch/riscv/dts/ae350_64.dts | 229
3 files changed, 458 insertions(+), 229 deletions(-)
delete mode 100644 arch/riscv/dts/ae350.dts
create mode 100644 arch/riscv/dts/ae350_32.dts
create mode 100644 arch/riscv/dts/ae350_64.dts
diff --git a/arch/riscv/dts/ae350.dts b/arch/riscv/dts/ae350.dts
deleted file mode 100644
index e48c298..000
--- a/arch/riscv/dts/ae350.dts
+++ /dev/null
@@ -1,229 +0,0 @@
-/dts-v1/;
-
-/ {
- #address-cells = <2>;
- #size-cells = <2>;
- compatible = "andestech,ax25";
- model = "andestech,ax25";
-
- aliases {
- uart0 =
- spi0 =
- };
-
- chosen {
- bootargs = "console=ttyS0,38400n8 debug loglevel=7";
- stdout-path = "uart0:38400n8";
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- timebase-frequency = <6000>;
- CPU0: cpu@0 {
- device_type = "cpu";
- reg = <0>;
- status = "okay";
- compatible = "riscv";
- riscv,isa = "rv64imafdc";
- mmu-type = "riscv,sv39";
- clock-frequency = <6000>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <32>;
- CPU0_intc: interrupt-controller {
- #interrupt-cells = <1>;
- interrupt-controller;
- compatible = "riscv,cpu-intc";
- };
- };
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x 0x0 0x4000>;
- };
-
- soc {
- #address-cells = <2>;
- #size-cells = <2>;
- compatible = "andestech,riscv-ae350-soc";
- ranges;
-
- plic0: interrupt-controller@e400 {
- compatible = "riscv,plic0";
- #address-cells = <2>;
- #interrupt-cells = <2>;
- interrupt-controller;
- reg = <0x0 0xe400 0x0 0x200>;
- riscv,ndev=<71>;
- interrupts-extended = <_intc 11 _intc 9>;
- };
-
- plic1: interrupt-controller@e640 {
- compatible = "riscv,plic1";
- #address-cells = <2>;
- #interrupt-cells = <2>;
- interrupt-controller;
- reg = <0x0 0xe640 0x0 0x40>;
- riscv,ndev=<1>;
- interrupts-extended = <_intc 3>;
- };
-
- plmt0@e600 {
- compatible = "riscv,plmt0";
- interrupts-extended = <_intc 7>;
- reg = <0x0 0xe600 0x0 0x10>;
- };
- };
-
- spiclk: virt_100mhz {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <1>;
- };
-
- timer0: timer@f040 {
- compatible = "andestech,atcpit100";
- reg = <0x0 0xf040 0x0 0x1000>;
- clock-frequency = <6000>;
- interrupts = <3 4>;
- interrupt-parent = <>;
- };
-
- serial0: serial@f030 {
- compatible = "andestech,uart16550", "ns16550a";
- reg = <0x0 0xf030 0x0 0x1000>;
- interrupts = <9 4>;
- clock-frequency = <19660800>;
- reg-shift = <2>;
- reg-offset = <32>;
- no-loopback-test = <1>;
- interrupt-parent = <>;
- };
-
- mac0: mac@e010 {
- compatible = "andestech,atmac100";
- reg = <0x0 0xe010 0x0 0x1000>;
- interrupts = <19 4>;
- interrupt-parent = <>;
- };
-
- mmc0: mmc@f0e0 {
- compatible = "andestech,atfsdc010";
- max-frequency = <1>;
- clock-freq-min-max = <40 1>;
- fifo-depth = <0x10>;
- reg = <0x0 0xf0e0 0x0 0x1000>;
- interrupts = <18 4>;
- cap-sd-highspeed;
- interrupt-parent = <>;
- };
-
- dma0: dma@f0c0 {
- compatible = "andestech,atcdmac300";
- reg = <0x0 0xf0c0 0x0 0x1000>;
- interrupts = <10 4 64 4 65 4 66 4 67 4 68 4 69 4 70 4 71 4>;
- dma-channels = <8>;
- interrupt-parent = <>;
- };
-
-
