The last two commits on this file have added bounce buffer handling
to indirect read and write transfers. However, these are cpu-only
transfers and bouncebuf seems to be written for dma transfers only
(it invalidates the dcache in bouncebuf_stop, which throws away data
copied by the cpu that are still in cache only).
The last two commits resulted in reading random data on mach-socfpga.
By using the new flag GEN_BB_NODMA, cadence_qspi is fixed on that
platform (although the 'Sync DT bindings with Linux' patches from
Jason Rush are still needed to make it work).
Signed-off-by: Simon Goldschmidt <sgoldschm...@de.pepperl-fuchs.com>
---
drivers/spi/cadence_qspi_apb.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 7d335519b0..a3e1c84758 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -645,7 +645,7 @@ int cadence_qspi_apb_indirect_read_execute(struct
cadence_spi_platdata *plat,
writel(CQSPI_REG_INDIRECTRD_START,
plat->regbase + CQSPI_REG_INDIRECTRD);
- ret = bounce_buffer_start(&bb, (void *)rxbuf, n_rx, GEN_BB_WRITE);
+ ret = bounce_buffer_start(&bb, (void *)rxbuf, n_rx,
GEN_BB_WRITE|GEN_BB_NODMA);
if (ret)
return ret;
bb_rxbuf = bb.bounce_buffer;
@@ -743,7 +743,7 @@ int cadence_qspi_apb_indirect_write_execute(struct
cadence_spi_platdata *plat,
* Handle non-4-byte aligned accesses via bounce buffer to
* avoid data abort.
*/
- ret = bounce_buffer_start(&bb, (void *)txbuf, n_tx, GEN_BB_READ);
+ ret = bounce_buffer_start(&bb, (void *)txbuf, n_tx,
GEN_BB_READ|GEN_BB_NODMA);
if (ret)
return ret;
bb_txbuf = bb.bounce_buffer;
--
2.12.2.windows.2
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