Re: [U-Boot] [PATCH 2/3] rockchip: add support for veyron-speedy (ASUS Chromebook C201)

[Dr. Philipp Tomsich]

> On 24 Jul 2018, at 07:12, Marty E. Plummer  wrote:
> 
> On Fri, Jul 13, 2018 at 12:31:49PM +0200, Dr. Philipp Tomsich wrote:
>> 
>>> On 7 May 2018, at 02:20, Marty E. Plummer  wrote:
>>> 
>>> On Mon, May 07, 2018 at 12:12:54AM +0200, klaus.go...@theobroma-systems.com 
>>>  wrote:
 
> On 06.05.2018, at 16:25, Marty E. Plummer  wrote:
> 
> This adds support for the ASUS C201, a RK3288-based clamshell
> device. The device tree comes from linus's linux tree at
> 87ef12027b9b1dd0e0b12cf311fbcb19f9d92539. The SDRAM parameters
> are for 4GB Samsung LPDDR3, decoded from coreboot's
> src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc
> 
> Signed-off-by: Marty E. Plummer 
> ---
> arch/arm/dts/Makefile |   1 +
> arch/arm/dts/rk3288-veyron-speedy.dts | 189 ++
> arch/arm/mach-rockchip/rk3288-board-spl.c |   3 +-
> arch/arm/mach-rockchip/rk3288/Kconfig |  11 ++
> board/google/veyron/Kconfig   |  16 ++
> configs/chromebook_speedy_defconfig   |  96 +++
> 6 files changed, 315 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/dts/rk3288-veyron-speedy.dts
> create mode 100644 configs/chromebook_speedy_defconfig
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index ac7667b1e8..ee04d9bedd 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -42,6 +42,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
>   rk3288-veyron-jerry.dtb \
>   rk3288-veyron-mickey.dtb \
>   rk3288-veyron-minnie.dtb \
> + rk3288-veyron-speedy.dtb \
>   rk3288-vyasa.dtb \
>   rk3328-evb.dtb \
>   rk3368-lion.dtb \
> diff --git a/arch/arm/dts/rk3288-veyron-speedy.dts 
> b/arch/arm/dts/rk3288-veyron-speedy.dts
> new file mode 100644
> index 00..d5383cef0d
> --- /dev/null
> +++ b/arch/arm/dts/rk3288-veyron-speedy.dts
 
 This file looks quite different then the one I see on kernel.org with that 
 revision id. So you are sure you
 imported that one?
>>> Dafuq... it seems I borked something up in doing the patch juggling to
>>> turn my single-commit mess of a patch (you know, the 'get the thing to
>>> work branch') into a good patch series I messed up on this one.
 
> @@ -0,0 +1,189 @@
> +/*
> + * Google Veyron Speedy Rev 1+ board device tree source
> + *
> + * Copyright 2015 Google, Inc
> + *
> + * SPDX-License-Identifier:  GPL-2.0
 
 This file is dual licensed upstream, keep it that way.
 The comment will claim it's a X11 license but the license text below
 is actually MIT so you may want to use the MIT SPDX tag for that.
 
>>> Yeah, I was listening in on the convo on irc. So, even though it 'says'
>>> its GPL/X11, the actual license text is MIT, so I should use that tag?
>>> Its not my code, obviously, so I have no dog in that race anyways.
> + */
> +
> +/dts-v1/;
> +#include "rk3288-veyron-chromebook.dtsi"
> +#include "cros-ec-sbs.dtsi"
> +
> +/ {
> + model = "Google Speedy";
> + compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8",
> +  "google,veyron-speedy-rev7", "google,veyron-speedy-rev6",
> +  "google,veyron-speedy-rev5", "google,veyron-speedy-rev4",
> +  "google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
> +  "google,veyron-speedy", "google,veyron", "rockchip,rk3288";
> +
> + chosen {
> + stdout-path = &uart2;
> + };
> +
> + panel_regulator: panel-regulator {
> + compatible = "regulator-fixed";
> + enable-active-high;
> + gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&lcd_enable_h>;
> + regulator-name = "panel_regulator";
> + startup-delay-us = <10>;
> + vin-supply = <&vcc33_sys>;
> + };
> +
> + vcc18_lcd: vcc18-lcd {
> + compatible = "regulator-fixed";
> + enable-active-high;
> + gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&avdd_1v8_disp_en>;
> + regulator-name = "vcc18_lcd";
> + regulator-always-on;
> + regulator-boot-on;
> + vin-supply = <&vcc18_wl>;
> + };
> +
> + backlight_regulator: backlight-regulator {
> + compatible = "regulator-fixed";
> + enable-active-high;
> + gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&bl_pwr_en>;
> + regulator-name = "backlight_regulator";
> + vin-supply = <&vcc33_sys>;
> + startup-delay-us = <15000>;
> + };
> 

Re: [U-Boot] [PATCH 2/3] rockchip: add support for veyron-speedy (ASUS Chromebook C201)

[Marty E. Plummer]

On Fri, Jul 13, 2018 at 12:31:49PM +0200, Dr. Philipp Tomsich wrote:
> 
> > On 7 May 2018, at 02:20, Marty E. Plummer  wrote:
> > 
> > On Mon, May 07, 2018 at 12:12:54AM +0200, klaus.go...@theobroma-systems.com 
> >  wrote:
> >> 
> >>> On 06.05.2018, at 16:25, Marty E. Plummer  wrote:
> >>> 
> >>> This adds support for the ASUS C201, a RK3288-based clamshell
> >>> device. The device tree comes from linus's linux tree at
> >>> 87ef12027b9b1dd0e0b12cf311fbcb19f9d92539. The SDRAM parameters
> >>> are for 4GB Samsung LPDDR3, decoded from coreboot's
> >>> src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc
> >>> 
> >>> Signed-off-by: Marty E. Plummer 
> >>> ---
> >>> arch/arm/dts/Makefile |   1 +
> >>> arch/arm/dts/rk3288-veyron-speedy.dts | 189 ++
> >>> arch/arm/mach-rockchip/rk3288-board-spl.c |   3 +-
> >>> arch/arm/mach-rockchip/rk3288/Kconfig |  11 ++
> >>> board/google/veyron/Kconfig   |  16 ++
> >>> configs/chromebook_speedy_defconfig   |  96 +++
> >>> 6 files changed, 315 insertions(+), 1 deletion(-)
> >>> create mode 100644 arch/arm/dts/rk3288-veyron-speedy.dts
> >>> create mode 100644 configs/chromebook_speedy_defconfig
> >>> 
> >>> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> >>> index ac7667b1e8..ee04d9bedd 100644
> >>> --- a/arch/arm/dts/Makefile
> >>> +++ b/arch/arm/dts/Makefile
> >>> @@ -42,6 +42,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
> >>>   rk3288-veyron-jerry.dtb \
> >>>   rk3288-veyron-mickey.dtb \
> >>>   rk3288-veyron-minnie.dtb \
> >>> + rk3288-veyron-speedy.dtb \
> >>>   rk3288-vyasa.dtb \
> >>>   rk3328-evb.dtb \
> >>>   rk3368-lion.dtb \
> >>> diff --git a/arch/arm/dts/rk3288-veyron-speedy.dts 
> >>> b/arch/arm/dts/rk3288-veyron-speedy.dts
> >>> new file mode 100644
> >>> index 00..d5383cef0d
> >>> --- /dev/null
> >>> +++ b/arch/arm/dts/rk3288-veyron-speedy.dts
> >> 
> >> This file looks quite different then the one I see on kernel.org with that 
> >> revision id. So you are sure you
> >> imported that one?
> > Dafuq... it seems I borked something up in doing the patch juggling to
> > turn my single-commit mess of a patch (you know, the 'get the thing to
> > work branch') into a good patch series I messed up on this one.
> >> 
> >>> @@ -0,0 +1,189 @@
> >>> +/*
> >>> + * Google Veyron Speedy Rev 1+ board device tree source
> >>> + *
> >>> + * Copyright 2015 Google, Inc
> >>> + *
> >>> + * SPDX-License-Identifier:  GPL-2.0
> >> 
> >> This file is dual licensed upstream, keep it that way.
> >> The comment will claim it's a X11 license but the license text below
> >> is actually MIT so you may want to use the MIT SPDX tag for that.
> >> 
> > Yeah, I was listening in on the convo on irc. So, even though it 'says'
> > its GPL/X11, the actual license text is MIT, so I should use that tag?
> > Its not my code, obviously, so I have no dog in that race anyways.
> >>> + */
> >>> +
> >>> +/dts-v1/;
> >>> +#include "rk3288-veyron-chromebook.dtsi"
> >>> +#include "cros-ec-sbs.dtsi"
> >>> +
> >>> +/ {
> >>> + model = "Google Speedy";
> >>> + compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8",
> >>> +  "google,veyron-speedy-rev7", "google,veyron-speedy-rev6",
> >>> +  "google,veyron-speedy-rev5", "google,veyron-speedy-rev4",
> >>> +  "google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
> >>> +  "google,veyron-speedy", "google,veyron", "rockchip,rk3288";
> >>> +
> >>> + chosen {
> >>> + stdout-path = &uart2;
> >>> + };
> >>> +
> >>> + panel_regulator: panel-regulator {
> >>> + compatible = "regulator-fixed";
> >>> + enable-active-high;
> >>> + gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
> >>> + pinctrl-names = "default";
> >>> + pinctrl-0 = <&lcd_enable_h>;
> >>> + regulator-name = "panel_regulator";
> >>> + startup-delay-us = <10>;
> >>> + vin-supply = <&vcc33_sys>;
> >>> + };
> >>> +
> >>> + vcc18_lcd: vcc18-lcd {
> >>> + compatible = "regulator-fixed";
> >>> + enable-active-high;
> >>> + gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
> >>> + pinctrl-names = "default";
> >>> + pinctrl-0 = <&avdd_1v8_disp_en>;
> >>> + regulator-name = "vcc18_lcd";
> >>> + regulator-always-on;
> >>> + regulator-boot-on;
> >>> + vin-supply = <&vcc18_wl>;
> >>> + };
> >>> +
> >>> + backlight_regulator: backlight-regulator {
> >>> + compatible = "regulator-fixed";
> >>> + enable-active-high;
> >>> + gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
> >>> + pinctrl-names = "default";
> >>> + pinctrl-0 = <&bl_pwr_en>;
> >>> + regulator-name = "backlight_regulator";
> >>> + vin-supply = <&vcc33_sys>;
> >>> + startup-delay-us = <15000>;
> >>> + };
> >>> +};
> >>> +
> >>> +&dmc {
> >>> + rockchip,pctl-timing = <0x

Re: [U-Boot] [PATCH 2/3] rockchip: add support for veyron-speedy (ASUS Chromebook C201)

[Dr. Philipp Tomsich]

> On 7 May 2018, at 02:20, Marty E. Plummer  wrote:
> 
> On Mon, May 07, 2018 at 12:12:54AM +0200, klaus.go...@theobroma-systems.com 
>  wrote:
>> 
>>> On 06.05.2018, at 16:25, Marty E. Plummer  wrote:
>>> 
>>> This adds support for the ASUS C201, a RK3288-based clamshell
>>> device. The device tree comes from linus's linux tree at
>>> 87ef12027b9b1dd0e0b12cf311fbcb19f9d92539. The SDRAM parameters
>>> are for 4GB Samsung LPDDR3, decoded from coreboot's
>>> src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc
>>> 
>>> Signed-off-by: Marty E. Plummer 
>>> ---
>>> arch/arm/dts/Makefile |   1 +
>>> arch/arm/dts/rk3288-veyron-speedy.dts | 189 ++
>>> arch/arm/mach-rockchip/rk3288-board-spl.c |   3 +-
>>> arch/arm/mach-rockchip/rk3288/Kconfig |  11 ++
>>> board/google/veyron/Kconfig   |  16 ++
>>> configs/chromebook_speedy_defconfig   |  96 +++
>>> 6 files changed, 315 insertions(+), 1 deletion(-)
>>> create mode 100644 arch/arm/dts/rk3288-veyron-speedy.dts
>>> create mode 100644 configs/chromebook_speedy_defconfig
>>> 
>>> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
>>> index ac7667b1e8..ee04d9bedd 100644
>>> --- a/arch/arm/dts/Makefile
>>> +++ b/arch/arm/dts/Makefile
>>> @@ -42,6 +42,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
>>> rk3288-veyron-jerry.dtb \
>>> rk3288-veyron-mickey.dtb \
>>> rk3288-veyron-minnie.dtb \
>>> +   rk3288-veyron-speedy.dtb \
>>> rk3288-vyasa.dtb \
>>> rk3328-evb.dtb \
>>> rk3368-lion.dtb \
>>> diff --git a/arch/arm/dts/rk3288-veyron-speedy.dts 
>>> b/arch/arm/dts/rk3288-veyron-speedy.dts
>>> new file mode 100644
>>> index 00..d5383cef0d
>>> --- /dev/null
>>> +++ b/arch/arm/dts/rk3288-veyron-speedy.dts
>> 
>> This file looks quite different then the one I see on kernel.org with that 
>> revision id. So you are sure you
>> imported that one?
> Dafuq... it seems I borked something up in doing the patch juggling to
> turn my single-commit mess of a patch (you know, the 'get the thing to
> work branch') into a good patch series I messed up on this one.
>> 
>>> @@ -0,0 +1,189 @@
>>> +/*
>>> + * Google Veyron Speedy Rev 1+ board device tree source
>>> + *
>>> + * Copyright 2015 Google, Inc
>>> + *
>>> + * SPDX-License-Identifier:GPL-2.0
>> 
>> This file is dual licensed upstream, keep it that way.
>> The comment will claim it's a X11 license but the license text below
>> is actually MIT so you may want to use the MIT SPDX tag for that.
>> 
> Yeah, I was listening in on the convo on irc. So, even though it 'says'
> its GPL/X11, the actual license text is MIT, so I should use that tag?
> Its not my code, obviously, so I have no dog in that race anyways.
>>> + */
>>> +
>>> +/dts-v1/;
>>> +#include "rk3288-veyron-chromebook.dtsi"
>>> +#include "cros-ec-sbs.dtsi"
>>> +
>>> +/ {
>>> +   model = "Google Speedy";
>>> +   compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8",
>>> +"google,veyron-speedy-rev7", "google,veyron-speedy-rev6",
>>> +"google,veyron-speedy-rev5", "google,veyron-speedy-rev4",
>>> +"google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
>>> +"google,veyron-speedy", "google,veyron", "rockchip,rk3288";
>>> +
>>> +   chosen {
>>> +   stdout-path = &uart2;
>>> +   };
>>> +
>>> +   panel_regulator: panel-regulator {
>>> +   compatible = "regulator-fixed";
>>> +   enable-active-high;
>>> +   gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
>>> +   pinctrl-names = "default";
>>> +   pinctrl-0 = <&lcd_enable_h>;
>>> +   regulator-name = "panel_regulator";
>>> +   startup-delay-us = <10>;
>>> +   vin-supply = <&vcc33_sys>;
>>> +   };
>>> +
>>> +   vcc18_lcd: vcc18-lcd {
>>> +   compatible = "regulator-fixed";
>>> +   enable-active-high;
>>> +   gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
>>> +   pinctrl-names = "default";
>>> +   pinctrl-0 = <&avdd_1v8_disp_en>;
>>> +   regulator-name = "vcc18_lcd";
>>> +   regulator-always-on;
>>> +   regulator-boot-on;
>>> +   vin-supply = <&vcc18_wl>;
>>> +   };
>>> +
>>> +   backlight_regulator: backlight-regulator {
>>> +   compatible = "regulator-fixed";
>>> +   enable-active-high;
>>> +   gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
>>> +   pinctrl-names = "default";
>>> +   pinctrl-0 = <&bl_pwr_en>;
>>> +   regulator-name = "backlight_regulator";
>>> +   vin-supply = <&vcc33_sys>;
>>> +   startup-delay-us = <15000>;
>>> +   };
>>> +};
>>> +
>>> +&dmc {
>>> +   rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
>>> +   0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
>>> +   0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
>>> +   0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
>>> +   0x8 0x1f4>

Re: [U-Boot] [PATCH 2/3] rockchip: add support for veyron-speedy (ASUS Chromebook C201)

[Marty E. Plummer]

On Mon, May 07, 2018 at 12:12:54AM +0200, klaus.go...@theobroma-systems.com 
wrote:
> 
> > On 06.05.2018, at 16:25, Marty E. Plummer  wrote:
> > 
> > This adds support for the ASUS C201, a RK3288-based clamshell
> > device. The device tree comes from linus's linux tree at
> > 87ef12027b9b1dd0e0b12cf311fbcb19f9d92539. The SDRAM parameters
> > are for 4GB Samsung LPDDR3, decoded from coreboot's
> > src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc
> > 
> > Signed-off-by: Marty E. Plummer 
> > ---
> > arch/arm/dts/Makefile |   1 +
> > arch/arm/dts/rk3288-veyron-speedy.dts | 189 ++
> > arch/arm/mach-rockchip/rk3288-board-spl.c |   3 +-
> > arch/arm/mach-rockchip/rk3288/Kconfig |  11 ++
> > board/google/veyron/Kconfig   |  16 ++
> > configs/chromebook_speedy_defconfig   |  96 +++
> > 6 files changed, 315 insertions(+), 1 deletion(-)
> > create mode 100644 arch/arm/dts/rk3288-veyron-speedy.dts
> > create mode 100644 configs/chromebook_speedy_defconfig
> > 
> > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> > index ac7667b1e8..ee04d9bedd 100644
> > --- a/arch/arm/dts/Makefile
> > +++ b/arch/arm/dts/Makefile
> > @@ -42,6 +42,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
> > rk3288-veyron-jerry.dtb \
> > rk3288-veyron-mickey.dtb \
> > rk3288-veyron-minnie.dtb \
> > +   rk3288-veyron-speedy.dtb \
> > rk3288-vyasa.dtb \
> > rk3328-evb.dtb \
> > rk3368-lion.dtb \
> > diff --git a/arch/arm/dts/rk3288-veyron-speedy.dts 
> > b/arch/arm/dts/rk3288-veyron-speedy.dts
> > new file mode 100644
> > index 00..d5383cef0d
> > --- /dev/null
> > +++ b/arch/arm/dts/rk3288-veyron-speedy.dts
> 
> This file looks quite different then the one I see on kernel.org with that 
> revision id. So you are sure you
> imported that one?
Dafuq... it seems I borked something up in doing the patch juggling to
turn my single-commit mess of a patch (you know, the 'get the thing to
work branch') into a good patch series I messed up on this one.
> 
> > @@ -0,0 +1,189 @@
> > +/*
> > + * Google Veyron Speedy Rev 1+ board device tree source
> > + *
> > + * Copyright 2015 Google, Inc
> > + *
> > + * SPDX-License-Identifier:GPL-2.0
> 
> This file is dual licensed upstream, keep it that way.
> The comment will claim it's a X11 license but the license text below
> is actually MIT so you may want to use the MIT SPDX tag for that.
> 
Yeah, I was listening in on the convo on irc. So, even though it 'says'
its GPL/X11, the actual license text is MIT, so I should use that tag?
Its not my code, obviously, so I have no dog in that race anyways.
> > + */
> > +
> > +/dts-v1/;
> > +#include "rk3288-veyron-chromebook.dtsi"
> > +#include "cros-ec-sbs.dtsi"
> > +
> > +/ {
> > +   model = "Google Speedy";
> > +   compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8",
> > +"google,veyron-speedy-rev7", "google,veyron-speedy-rev6",
> > +"google,veyron-speedy-rev5", "google,veyron-speedy-rev4",
> > +"google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
> > +"google,veyron-speedy", "google,veyron", "rockchip,rk3288";
> > +
> > +   chosen {
> > +   stdout-path = &uart2;
> > +   };
> > +
> > +   panel_regulator: panel-regulator {
> > +   compatible = "regulator-fixed";
> > +   enable-active-high;
> > +   gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
> > +   pinctrl-names = "default";
> > +   pinctrl-0 = <&lcd_enable_h>;
> > +   regulator-name = "panel_regulator";
> > +   startup-delay-us = <10>;
> > +   vin-supply = <&vcc33_sys>;
> > +   };
> > +
> > +   vcc18_lcd: vcc18-lcd {
> > +   compatible = "regulator-fixed";
> > +   enable-active-high;
> > +   gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
> > +   pinctrl-names = "default";
> > +   pinctrl-0 = <&avdd_1v8_disp_en>;
> > +   regulator-name = "vcc18_lcd";
> > +   regulator-always-on;
> > +   regulator-boot-on;
> > +   vin-supply = <&vcc18_wl>;
> > +   };
> > +
> > +   backlight_regulator: backlight-regulator {
> > +   compatible = "regulator-fixed";
> > +   enable-active-high;
> > +   gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
> > +   pinctrl-names = "default";
> > +   pinctrl-0 = <&bl_pwr_en>;
> > +   regulator-name = "backlight_regulator";
> > +   vin-supply = <&vcc33_sys>;
> > +   startup-delay-us = <15000>;
> > +   };
> > +};
> > +
> > +&dmc {
> > +   rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
> > +   0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
> > +   0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
> > +   0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
> > +   0x8 0x1f4>;
> > +   rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
> > +   0x0 0xc3 0x6 0x1>;
> > +   rockchip,sdram-para

Re: [U-Boot] [PATCH 2/3] rockchip: add support for veyron-speedy (ASUS Chromebook C201)

[klaus . goger]

> On 06.05.2018, at 16:25, Marty E. Plummer  wrote:
> 
> This adds support for the ASUS C201, a RK3288-based clamshell
> device. The device tree comes from linus's linux tree at
> 87ef12027b9b1dd0e0b12cf311fbcb19f9d92539. The SDRAM parameters
> are for 4GB Samsung LPDDR3, decoded from coreboot's
> src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc
> 
> Signed-off-by: Marty E. Plummer 
> ---
> arch/arm/dts/Makefile |   1 +
> arch/arm/dts/rk3288-veyron-speedy.dts | 189 ++
> arch/arm/mach-rockchip/rk3288-board-spl.c |   3 +-
> arch/arm/mach-rockchip/rk3288/Kconfig |  11 ++
> board/google/veyron/Kconfig   |  16 ++
> configs/chromebook_speedy_defconfig   |  96 +++
> 6 files changed, 315 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/dts/rk3288-veyron-speedy.dts
> create mode 100644 configs/chromebook_speedy_defconfig
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index ac7667b1e8..ee04d9bedd 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -42,6 +42,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
>   rk3288-veyron-jerry.dtb \
>   rk3288-veyron-mickey.dtb \
>   rk3288-veyron-minnie.dtb \
> + rk3288-veyron-speedy.dtb \
>   rk3288-vyasa.dtb \
>   rk3328-evb.dtb \
>   rk3368-lion.dtb \
> diff --git a/arch/arm/dts/rk3288-veyron-speedy.dts 
> b/arch/arm/dts/rk3288-veyron-speedy.dts
> new file mode 100644
> index 00..d5383cef0d
> --- /dev/null
> +++ b/arch/arm/dts/rk3288-veyron-speedy.dts

This file looks quite different then the one I see on kernel.org with that 
revision id. So you are sure you
imported that one?

> @@ -0,0 +1,189 @@
> +/*
> + * Google Veyron Speedy Rev 1+ board device tree source
> + *
> + * Copyright 2015 Google, Inc
> + *
> + * SPDX-License-Identifier:  GPL-2.0

This file is dual licensed upstream, keep it that way.
The comment will claim it’s a X11 license but the license text below
is actually MIT so you may want to use the MIT SPDX tag for that.

> + */
> +
> +/dts-v1/;
> +#include "rk3288-veyron-chromebook.dtsi"
> +#include "cros-ec-sbs.dtsi"
> +
> +/ {
> + model = "Google Speedy";
> + compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8",
> +  "google,veyron-speedy-rev7", "google,veyron-speedy-rev6",
> +  "google,veyron-speedy-rev5", "google,veyron-speedy-rev4",
> +  "google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
> +  "google,veyron-speedy", "google,veyron", "rockchip,rk3288";
> +
> + chosen {
> + stdout-path = &uart2;
> + };
> +
> + panel_regulator: panel-regulator {
> + compatible = "regulator-fixed";
> + enable-active-high;
> + gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&lcd_enable_h>;
> + regulator-name = "panel_regulator";
> + startup-delay-us = <10>;
> + vin-supply = <&vcc33_sys>;
> + };
> +
> + vcc18_lcd: vcc18-lcd {
> + compatible = "regulator-fixed";
> + enable-active-high;
> + gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&avdd_1v8_disp_en>;
> + regulator-name = "vcc18_lcd";
> + regulator-always-on;
> + regulator-boot-on;
> + vin-supply = <&vcc18_wl>;
> + };
> +
> + backlight_regulator: backlight-regulator {
> + compatible = "regulator-fixed";
> + enable-active-high;
> + gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&bl_pwr_en>;
> + regulator-name = "backlight_regulator";
> + vin-supply = <&vcc33_sys>;
> + startup-delay-us = <15000>;
> + };
> +};
> +
> +&dmc {
> + rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
> + 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
> + 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
> + 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
> + 0x8 0x1f4>;
> + rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
> + 0x0 0xc3 0x6 0x1>;
> + rockchip,sdram-params = <0x20D266A4 0x5B6 6 53300 6 13 0>;
> +};

Not sure if this should go into a separate dtsi. One of the maintainer will have
a preferred way I think, so lets see what they will add.

> +&gpio_keys {
> + power {
> + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
> + };
> +};
> +
> +&backlight {
> + power-supply = <&backlight_regulator>;
> +};
> +
> +&panel {
> + power-supply = <&panel_regulator>;
> +};
> +
> +&rk808 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pmic_int_l>;
> +};
> +
> +&sdmmc {
> + pinctrl-names = "default";
> + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_di

[U-Boot] [PATCH 2/3] rockchip: add support for veyron-speedy (ASUS Chromebook C201)

[Marty E. Plummer]

This adds support for the ASUS C201, a RK3288-based clamshell
device. The device tree comes from linus's linux tree at
87ef12027b9b1dd0e0b12cf311fbcb19f9d92539. The SDRAM parameters
are for 4GB Samsung LPDDR3, decoded from coreboot's
src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc

Signed-off-by: Marty E. Plummer 
---
 arch/arm/dts/Makefile |   1 +
 arch/arm/dts/rk3288-veyron-speedy.dts | 189 ++
 arch/arm/mach-rockchip/rk3288-board-spl.c |   3 +-
 arch/arm/mach-rockchip/rk3288/Kconfig |  11 ++
 board/google/veyron/Kconfig   |  16 ++
 configs/chromebook_speedy_defconfig   |  96 +++
 6 files changed, 315 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/rk3288-veyron-speedy.dts
 create mode 100644 configs/chromebook_speedy_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ac7667b1e8..ee04d9bedd 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -42,6 +42,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-veyron-jerry.dtb \
rk3288-veyron-mickey.dtb \
rk3288-veyron-minnie.dtb \
+   rk3288-veyron-speedy.dtb \
rk3288-vyasa.dtb \
rk3328-evb.dtb \
rk3368-lion.dtb \
diff --git a/arch/arm/dts/rk3288-veyron-speedy.dts 
b/arch/arm/dts/rk3288-veyron-speedy.dts
new file mode 100644
index 00..d5383cef0d
--- /dev/null
+++ b/arch/arm/dts/rk3288-veyron-speedy.dts
@@ -0,0 +1,189 @@
+/*
+ * Google Veyron Speedy Rev 1+ board device tree source
+ *
+ * Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+/dts-v1/;
+#include "rk3288-veyron-chromebook.dtsi"
+#include "cros-ec-sbs.dtsi"
+
+/ {
+   model = "Google Speedy";
+   compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8",
+"google,veyron-speedy-rev7", "google,veyron-speedy-rev6",
+"google,veyron-speedy-rev5", "google,veyron-speedy-rev4",
+"google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
+"google,veyron-speedy", "google,veyron", "rockchip,rk3288";
+
+   chosen {
+   stdout-path = &uart2;
+   };
+
+   panel_regulator: panel-regulator {
+   compatible = "regulator-fixed";
+   enable-active-high;
+   gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&lcd_enable_h>;
+   regulator-name = "panel_regulator";
+   startup-delay-us = <10>;
+   vin-supply = <&vcc33_sys>;
+   };
+
+   vcc18_lcd: vcc18-lcd {
+   compatible = "regulator-fixed";
+   enable-active-high;
+   gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&avdd_1v8_disp_en>;
+   regulator-name = "vcc18_lcd";
+   regulator-always-on;
+   regulator-boot-on;
+   vin-supply = <&vcc18_wl>;
+   };
+
+   backlight_regulator: backlight-regulator {
+   compatible = "regulator-fixed";
+   enable-active-high;
+   gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&bl_pwr_en>;
+   regulator-name = "backlight_regulator";
+   vin-supply = <&vcc33_sys>;
+   startup-delay-us = <15000>;
+   };
+};
+
+&dmc {
+   rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
+   0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
+   0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
+   0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
+   0x8 0x1f4>;
+   rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
+   0x0 0xc3 0x6 0x1>;
+   rockchip,sdram-params = <0x20D266A4 0x5B6 6 53300 6 13 0>;
+};
+
+&gpio_keys {
+   power {
+   gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+   };
+};
+
+&backlight {
+   power-supply = <&backlight_regulator>;
+};
+
+&panel {
+   power-supply = <&panel_regulator>;
+};
+
+&rk808 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pmic_int_l>;
+};
+
+&sdmmc {
+   pinctrl-names = "default";
+   pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
+   &sdmmc_bus4>;
+   disable-wp;
+};
+
+&vcc_5v {
+   enable-active-high;
+   gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&drv_5v>;
+};
+
+&vcc50_hdmi {
+   enable-active-high;
+   gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&vcc50_hdmi_en>;
+};
+
+&edp {
+   pinctrl-names = "default";
+   pinctrl-0 = <&edp_hpd>;
+};
+
+&pinctrl {
+   backlight {
+   bl_pwr_en: bl_pwr_en {
+   rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg