This patch adds support for the mvpp2 ethernet controller which is integrated
in the Marvell Armada 375 SoC. This port is based on the Linux driver (v4.4),
which has been stripped of the in U-Boot unused portions.
Tested on the Marvell Armada 375 eval board db-88f6720.
Signed-off-by: Stefan Roese
Cc: Luka Perkov
Cc: Joe Hershberger
---
v3:
- Use priv_auto_alloc for the priv struct of the parent MISC
driver instead of allocating manually
v2:
- Removed check for PHYLIB
- Used U-Boot defines instead of Linux ones where possible
- Added PROT_PPP_SES and PROT_IPV6 to include/net.h
- Introduced probe function for the MISC parent driver, which
now handles all the "do-once" things
drivers/net/Kconfig |8 +
drivers/net/Makefile |1 +
drivers/net/mvpp2.c | 4190 ++
include/net.h|2 +
4 files changed, 4201 insertions(+)
create mode 100644 drivers/net/mvpp2.c
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 2a229b8..d9dda16 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -94,6 +94,14 @@ config ETH_DESIGNWARE
100Mbit and 1 Gbit operation. You must enable CONFIG_PHYLIB to
provide the PHY (physical media interface).
+config MVPP2
+ bool "Marvell Armada 375 network interface support"
+ depends on ARMADA_375
+ select PHYLIB
+ help
+ This driver supports the network interface units in the
+ Marvell ARMADA 375 SoC.
+
config PCH_GBE
bool "Intel Platform Controller Hub EG20T GMAC driver"
depends on DM_ETH && DM_PCI
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 33a81ee..fbedd04 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o
obj-$(CONFIG_MPC512x_FEC) += mpc512x_fec.o
obj-$(CONFIG_MVGBE) += mvgbe.o
obj-$(CONFIG_MVNETA) += mvneta.o
+obj-$(CONFIG_MVPP2) += mvpp2.o
obj-$(CONFIG_NATSEMI) += natsemi.o
obj-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o
obj-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o
diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
new file mode 100644
index 000..900a04c
--- /dev/null
+++ b/drivers/net/mvpp2.c
@@ -0,0 +1,4190 @@
+/*
+ * Driver for Marvell PPv2 network controller for Armada 375 SoC.
+ *
+ * Copyright (C) 2014 Marvell
+ *
+ * Marcin Wojtas
+ *
+ * U-Boot version:
+ * Copyright (C) 2016 Stefan Roese
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Some linux -> U-Boot compatibility stuff */
+#define netdev_err(dev, fmt, args...) \
+ printf(fmt, ##args)
+#define netdev_warn(dev, fmt, args...) \
+ printf(fmt, ##args)
+#define netdev_info(dev, fmt, args...) \
+ printf(fmt, ##args)
+#define netdev_dbg(dev, fmt, args...) \
+ printf(fmt, ##args)
+
+#define ETH_ALEN 6 /* Octets in one ethernet addr */
+
+#define __verify_pcpu_ptr(ptr) \
+do { \
+ const void __percpu *__vpp_verify = (typeof((ptr) + 0))NULL;\
+ (void)__vpp_verify; \
+} while (0)
+
+#define VERIFY_PERCPU_PTR(__p) \
+({ \
+ __verify_pcpu_ptr(__p); \
+ (typeof(*(__p)) __kernel __force *)(__p); \
+})
+
+#define per_cpu_ptr(ptr, cpu) ({ (void)(cpu); VERIFY_PERCPU_PTR(ptr); })
+#define smp_processor_id() 0
+#define num_present_cpus() 1
+#define for_each_present_cpu(cpu) \
+ for ((cpu) = 0; (cpu) < 1; (cpu)++)
+
+#define NET_SKB_PADmax(32, MVPP2_CPU_D_CACHE_LINE_SIZE)
+
+#define CONFIG_NR_CPUS 1
+#define ETH_HLEN ETHER_HDR_SIZE /* Total octets in header */
+
+/* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
+#define WRAP (2 + ETH_HLEN + 4 + 32)
+#define MTU1500
+#define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
+
+#define MVPP2_SMI_TIMEOUT 1
+
+/* RX Fifo Registers */
+#define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
+#define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
+#define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
+#define MVPP2_RX_FIFO_INIT_REG 0x64
+
+/* RX DMA Top Registers */
+#define MVPP2_RX_CTRL_REG(port)(0x140 + 4 * (po
