PRCM register addresses are changed from OMAP5 ES2.0 to DRA7XX.
So adding the necessary register changes for DRA7XX socs.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: R Sricharan r.sricha...@ti.com
---
arch/arm/cpu/armv7/omap4/hw_data.c |2 +-
arch/arm/cpu/armv7/omap4/prcm-regs.c |2 +-
arch/arm/cpu/armv7/omap5/hw_data.c |6 +-
arch/arm/cpu/armv7/omap5/prcm-regs.c | 218 +++-
arch/arm/include/asm/arch-omap5/cpu.h |4 +
arch/arm/include/asm/arch-omap5/omap.h |9 +-
arch/arm/include/asm/omap_common.h | 15 ++-
7 files changed, 249 insertions(+), 7 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c
b/arch/arm/cpu/armv7/omap4/hw_data.c
index 8d31d6d..3b27bc1 100644
--- a/arch/arm/cpu/armv7/omap4/hw_data.c
+++ b/arch/arm/cpu/armv7/omap4/hw_data.c
@@ -290,7 +290,7 @@ void enable_basic_clocks(void)
};
u32 const clk_modules_hw_auto_essential[] = {
- (*prcm)-cm_l3_2_gpmc_clkctrl,
+ (*prcm)-cm_l3_gpmc_clkctrl,
(*prcm)-cm_memif_emif_1_clkctrl,
(*prcm)-cm_memif_emif_2_clkctrl,
(*prcm)-cm_l4cfg_l4_cfg_clkctrl,
diff --git a/arch/arm/cpu/armv7/omap4/prcm-regs.c
b/arch/arm/cpu/armv7/omap4/prcm-regs.c
index c58ce8d..7225a30 100644
--- a/arch/arm/cpu/armv7/omap4/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap4/prcm-regs.c
@@ -153,7 +153,7 @@ struct prcm_regs const omap4_prcm = {
.cm_l3_2_clkstctrl = 0x4a008800,
.cm_l3_2_dynamicdep = 0x4a008808,
.cm_l3_2_l3_2_clkctrl = 0x4a008820,
- .cm_l3_2_gpmc_clkctrl = 0x4a008828,
+ .cm_l3_gpmc_clkctrl = 0x4a008828,
.cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
.cm_mpu_m3_clkstctrl = 0x4a008900,
.cm_mpu_m3_staticdep = 0x4a008904,
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c
b/arch/arm/cpu/armv7/omap5/hw_data.c
index 1701b09..22590f4 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -278,7 +278,7 @@ void enable_basic_clocks(void)
};
u32 const clk_modules_hw_auto_essential[] = {
- (*prcm)-cm_l3_2_gpmc_clkctrl,
+ (*prcm)-cm_l3_gpmc_clkctrl,
(*prcm)-cm_memif_emif_1_clkctrl,
(*prcm)-cm_memif_emif_2_clkctrl,
(*prcm)-cm_l4cfg_l4_cfg_clkctrl,
@@ -503,6 +503,10 @@ void hw_data_init(void)
*omap_vcores = omap5430_volts_es2;
break;
+ case DRA752_ES1_0:
+ *prcm = dra7xx_prcm;
+ break;
+
default:
printf(\n INVALID OMAP REVISION );
}
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c
b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index 5e5abcc..c8f62d1 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -156,7 +156,7 @@ struct prcm_regs const omap5_es1_prcm = {
.cm_l3_2_clkstctrl = 0x4a008800,
.cm_l3_2_dynamicdep = 0x4a008808,
.cm_l3_2_l3_2_clkctrl = 0x4a008820,
- .cm_l3_2_gpmc_clkctrl = 0x4a008828,
+ .cm_l3_gpmc_clkctrl = 0x4a008828,
.cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
.cm_mpu_m3_clkstctrl = 0x4a008900,
.cm_mpu_m3_staticdep = 0x4a008904,
@@ -513,7 +513,7 @@ struct prcm_regs const omap5_es2_prcm = {
.cm_l3_2_clkstctrl = 0x4a008800,
.cm_l3_2_dynamicdep = 0x4a008808,
.cm_l3_2_l3_2_clkctrl = 0x4a008820,
- .cm_l3_2_gpmc_clkctrl = 0x4a008828,
+ .cm_l3_gpmc_clkctrl = 0x4a008828,
.cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
.cm_mpu_m3_clkstctrl = 0x4a008900,
.cm_mpu_m3_staticdep = 0x4a008904,
@@ -664,3 +664,217 @@ struct prcm_regs const omap5_es2_prcm = {
.prm_sldo_mm_setup = 0x4ae07cd4,
.prm_sldo_mm_ctrl = 0x4ae07cd8,
};
+
+struct prcm_regs const dra7xx_prcm = {
+ /* cm1.ckgen */
+ .cm_clksel_core = 0x4a005100,
+ .cm_clksel_abe = 0x4a005108,
+ .cm_dll_ctrl= 0x4a005110,
+ .cm_clkmode_dpll_core = 0x4a005120,
+ .cm_idlest_dpll_core= 0x4a005124,
+ .cm_autoidle_dpll_core = 0x4a005128,
+ .cm_clksel_dpll_core= 0x4a00512c,
+ .cm_div_m2_dpll_core= 0x4a005130,
+ .cm_div_m3_dpll_core= 0x4a005134,
+ .cm_div_h11_dpll_core = 0x4a005138,
+ .cm_div_h12_dpll_core = 0x4a00513c,
+ .cm_div_h13_dpll_core = 0x4a005140,
+ .cm_div_h14_dpll_core = 0x4a005144,
+ .cm_ssc_deltamstep_dpll_core= 0x4a005148,
+ .cm_ssc_modfreqdiv_dpll_core= 0x4a00514c,
+ .cm_div_h21_dpll_core = 0x4a005150,
+ .cm_div_h22_dpllcore= 0x4a005154,
+ .cm_div_h23_dpll_core = 0x4a005158,
+
