[U-Boot] [PATCH 3/3] i.mx6q: arm2: Add the enet function support
This enable the network function on the i.mx6q armadillo2
board(arm2), thus we can use tftp to load image from network.
Cc: Stefano Babic
Signed-off-by: Jason Liu
Tested-by: Dirk Behme
---
board/freescale/mx6qarm2/mx6qarm2.c | 90 +++
include/configs/mx6qarm2.h | 13 -
2 files changed, 101 insertions(+), 2 deletions(-)
diff --git a/board/freescale/mx6qarm2/mx6qarm2.c
b/board/freescale/mx6qarm2/mx6qarm2.c
index 89e0e76..1df063a 100644
--- a/board/freescale/mx6qarm2/mx6qarm2.c
+++ b/board/freescale/mx6qarm2/mx6qarm2.c
@@ -29,6 +29,8 @@
#include
#include
#include
+#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -40,6 +42,10 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |\
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -79,11 +85,35 @@ iomux_v3_cfg_t usdhc4_pads[] = {
MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
+iomux_v3_cfg_t enet_pads[] = {
+ MX6Q_PAD_KEY_COL1__ENET_MDIO| MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
}
+static void setup_iomux_enet(void)
+{
+ imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+}
+
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC3_BASE_ADDR, 1},
@@ -132,9 +162,69 @@ int board_mmc_init(bd_t *bis)
}
#endif
+#define MII_MMD_ACCESS_CTRL_REG0xd
+#define MII_MMD_ACCESS_ADDR_DATA_REG 0xe
+#define MII_DBG_PORT_REG 0x1d
+#define MII_DBG_PORT2_REG 0x1e
+
+int fecmxc_mii_postcall(int phy)
+{
+ unsigned short val;
+
+ /*
+* Due to the i.MX6Q Armadillo2 board HW design,there is
+* no 125Mhz clock input from SOC. In order to use RGMII,
+* We need enable AR8031 ouput a 125MHz clk from CLK_25M
+*/
+ miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x7);
+ miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, 0x8016);
+ miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x4007);
+ miiphy_read("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, &val);
+ val &= 0xffe3;
+ val |= 0x18;
+ miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, val);
+
+ /* For the RGMII phy, we need enable tx clock delay */
+ miiphy_write("FEC", phy, 0x1d, 0x5);
+ miiphy_read("FEC", phy, 0x1e, &val);
+ val |= 0x0100;
+ miiphy_write("FEC", phy, 0x1e, val);
+
+ miiphy_write("FEC", phy, MII_BMCR, 0xa100);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ struct eth_device *dev;
+ int ret;
+
+ ret = cpu_eth_init(bis);
+ if (ret) {
+ printf("FEC MXC: %s:failed\n", __func__);
+ return ret;
+ }
+
+ dev = eth_get_dev_by_name("FEC");
+ if (!dev) {
+ printf("FEC MXC: Unable to get FEC device entry\n");
+ return -EINVAL;
+ }
+
+ ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
+ if (ret) {
+ printf("FEC MXC: Unable to register FEC mii postcall\n");
+ return ret;
+ }
+
+ return 0;
+}
+
int board_early_init_f(void)
{
setup_iomux_uart();
+ setup_iomux_enet();
return 0;
}
diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h
index a7b363d..3a30679 100644
--- a/include/configs/mx6qarm2.h
+++ b/include/configs/mx6qarm2.h
@@ -56,6 +56,17 @@
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_PIN
Re: [U-Boot] [PATCH 3/3] i.mx6q: arm2: Add the enet function support
On 13/12/2011 14:44, Jason Liu wrote:
> This enable the network function on the i.mx6q armadillo2
> board(arm2), thus we can use tftp to load image from network.
>
> Cc: Stefano Babic
> Signed-off-by: Jason Liu
> Tested-by: Dirk Behme
> ---
> board/freescale/mx6qarm2/mx6qarm2.c | 90
> +++
> include/configs/mx6qarm2.h | 13 -
> 2 files changed, 101 insertions(+), 2 deletions(-)
>
Hi Jason,
only a couple of minor issues.
> +
> #ifdef CONFIG_FSL_ESDHC
> struct fsl_esdhc_cfg usdhc_cfg[2] = {
> {USDHC3_BASE_ADDR, 1},
> @@ -132,9 +162,69 @@ int board_mmc_init(bd_t *bis)
> }
> #endif
>
> +#define MII_MMD_ACCESS_CTRL_REG 0xd
> +#define MII_MMD_ACCESS_ADDR_DATA_REG 0xe
> +#define MII_DBG_PORT_REG 0x1d
> +#define MII_DBG_PORT2_REG0x1e
> +
> +int fecmxc_mii_postcall(int phy)
> +{
> + unsigned short val;
> +
> + /*
> + * Due to the i.MX6Q Armadillo2 board HW design,there is
> + * no 125Mhz clock input from SOC. In order to use RGMII,
> + * We need enable AR8031 ouput a 125MHz clk from CLK_25M
> + */
> + miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x7);
> + miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, 0x8016);
> + miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x4007);
> + miiphy_read("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, &val);
> + val &= 0xffe3;
> + val |= 0x18;
> + miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, val);
> +
> + /* For the RGMII phy, we need enable tx clock delay */
> + miiphy_write("FEC", phy, 0x1d, 0x5);
You define MII_DBG_PORT_REG, but then you do not use it.
> + miiphy_read("FEC", phy, 0x1e, &val);
The same here for MII_DBG_PORT2_REG. Can you also defines some constants
for the value you are setting (tx clock delay, etc.).
> diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h
> index a7b363d..3a30679 100644
> --- a/include/configs/mx6qarm2.h
> +++ b/include/configs/mx6qarm2.h
> @@ -56,6 +56,17 @@
> #define CONFIG_CMD_FAT
> #define CONFIG_DOS_PARTITION
>
> +#define CONFIG_CMD_PING
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_MII
> +#define CONFIG_CMD_NET
> +#define CONFIG_FEC_MXC
> +#define CONFIG_MII
> +#define IMX_FEC_BASE ENET_BASE_ADDR
> +#define CONFIG_FEC_XCV_TYPE RGMII
> +#define CONFIG_ETHPRIME "FEC"
I have not thought this is needed. I see only one controller.
Best regards,
Stefano Babic
--
=
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: off...@denx.de
=
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Re: [U-Boot] [PATCH 3/3] i.mx6q: arm2: Add the enet function support
>-Original Message-
>From: u-boot-boun...@lists.denx.de [mailto:u-boot-boun...@lists.denx.de]
>On Behalf Of Stefano Babic
>Sent: Friday, December 16, 2011 7:30 PM
>To: Jason Liu
>Cc: u-boot@lists.denx.de
>Subject: Re: [U-Boot] [PATCH 3/3] i.mx6q: arm2: Add the enet function
>support
>
>On 13/12/2011 14:44, Jason Liu wrote:
>> This enable the network function on the i.mx6q armadillo2 board(arm2),
>> thus we can use tftp to load image from network.
>>
>> Cc: Stefano Babic
>> Signed-off-by: Jason Liu
>> Tested-by: Dirk Behme
>> ---
>> board/freescale/mx6qarm2/mx6qarm2.c | 90
>+++
>> include/configs/mx6qarm2.h | 13 -
>> 2 files changed, 101 insertions(+), 2 deletions(-)
>>
>
>Hi Jason,
>
>only a couple of minor issues.
Thanks for the review.
>
>> +
>> #ifdef CONFIG_FSL_ESDHC
>> struct fsl_esdhc_cfg usdhc_cfg[2] = {
>> {USDHC3_BASE_ADDR, 1},
>> @@ -132,9 +162,69 @@ int board_mmc_init(bd_t *bis) } #endif
>>
>> +#define MII_MMD_ACCESS_CTRL_REG 0xd
>> +#define MII_MMD_ACCESS_ADDR_DATA_REG0xe
>> +#define MII_DBG_PORT_REG0x1d
>> +#define MII_DBG_PORT2_REG 0x1e
>> +
>> +int fecmxc_mii_postcall(int phy)
>> +{
>> +unsigned short val;
>> +
>> +/*
>> + * Due to the i.MX6Q Armadillo2 board HW design,there is
>> + * no 125Mhz clock input from SOC. In order to use RGMII,
>> + * We need enable AR8031 ouput a 125MHz clk from CLK_25M
>> + */
>> +miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x7);
>> +miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG,
>0x8016);
>> +miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x4007);
>> +miiphy_read("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, &val);
>> +val &= 0xffe3;
>> +val |= 0x18;
>> +miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, val);
>> +
>> +/* For the RGMII phy, we need enable tx clock delay */
>> +miiphy_write("FEC", phy, 0x1d, 0x5);
>
>You define MII_DBG_PORT_REG, but then you do not use it.
>
>> +miiphy_read("FEC", phy, 0x1e, &val);
>
>The same here for MII_DBG_PORT2_REG. Can you also defines some
>constants for the value you are setting (tx clock delay, etc.).
Yeah, thanks for it. I will use MII_DBG_PORT_REG and MII_DBG_PORT2_REG.
>
>> diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h
>> index a7b363d..3a30679 100644
>> --- a/include/configs/mx6qarm2.h
>> +++ b/include/configs/mx6qarm2.h
>> @@ -56,6 +56,17 @@
>> #define CONFIG_CMD_FAT
>> #define CONFIG_DOS_PARTITION
>>
>> +#define CONFIG_CMD_PING
>> +#define CONFIG_CMD_DHCP
>> +#define CONFIG_CMD_MII
>> +#define CONFIG_CMD_NET
>> +#define CONFIG_FEC_MXC
>> +#define CONFIG_MII
>> +#define IMX_FEC_BASEENET_BASE_ADDR
>> +#define CONFIG_FEC_XCV_TYPE RGMII
>> +#define CONFIG_ETHPRIME "FEC"
>
>I have not thought this is needed. I see only one controller.
Yes, I think we can remove it.
Best regards,
Jason Liu
>
>Best regards,
>Stefano Babic
>
>--
>=
>
>DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
>HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
>Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: off...@denx.de
>=
>
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