[U-Boot] [PATCH 3/4] arm: zynq: Add Nand flash mini u-boot configuration for zynq
Add configuration files/dtses for mini u-boot configuration which runs on smaller footprint of memory. This configuration has only required nand flash support. Signed-off-by: Siva Durga Prasad Paladugu --- arch/arm/dts/Makefile | 1 + arch/arm/dts/zynq-cse-nand.dts | 90 + configs/zynq_cse_nand_defconfig | 50 +++ 3 files changed, 141 insertions(+) create mode 100644 arch/arm/dts/zynq-cse-nand.dts create mode 100644 configs/zynq_cse_nand_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a0349a8..71b7c3a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -128,6 +128,7 @@ dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \ dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-cc108.dtb \ + zynq-cse-nand.dtb \ zynq-cse-qspi-single.dtb \ zynq-microzed.dtb \ zynq-picozed.dtb \ diff --git a/arch/arm/dts/zynq-cse-nand.dts b/arch/arm/dts/zynq-cse-nand.dts new file mode 100644 index 000..9df5f9a --- /dev/null +++ b/arch/arm/dts/zynq-cse-nand.dts @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx CSE NAND board DTS + * + * Copyright (C) 2018 Xilinx, Inc. + */ +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "Zynq CSE NAND Board"; + compatible = "xlnx,zynq-cse-nand", "xlnx,zynq-7000"; + + aliases { + serial0 = &dcc; + }; + + memory@fffc { + device_type = "memory"; + reg = <0x0 0x40>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + dcc: dcc { + compatible = "arm,dcc"; + status = "disabled"; + u-boot,dm-pre-reloc; + }; + + amba: amba { + u-boot,dm-pre-reloc; + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + ranges; + + intc: interrupt-controller@f8f01000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xF8F01000 0x1000>, + <0xF8F00100 0x100>; + }; + + slcr: slcr@f800 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,zynq-slcr", "syscon", "simple-bus"; + reg = <0xF800 0x1000>; + ranges; + clkc: clkc@100 { + u-boot,dm-pre-reloc; + #clock-cells = <1>; + compatible = "xlnx,ps7-clkc"; + fclk-enable = <0xf>; + clock-output-names = "armpll", "ddrpll", + "iopll", "cpu_6or4x", + "cpu_3or2x", "cpu_2x", "cpu_1x", + "ddr2x", "ddr3x", "dci", + "lqspi", "smc", "pcap", "gem0", + "gem1", "fclk0", "fclk1", + "fclk2", "fclk3", "can0", + "can1", "sdio0", "sdio1", + "uart0", "uart1", "spi0", + "spi1", "dma", "usb0_aper", + "usb1_aper", "gem0_aper", + "gem1_aper", "sdio0_aper", + "sdio1_aper", "spi0_aper", + "spi1_aper", "can0_aper", + "can1_aper", "i2c0_aper", + "i2c1_aper", "uart0_aper", + "uart1_aper", "gpio_aper", + "lqspi_aper", "smc_aper", + "swdt", "dbg_trc", "dbg_apb"; + reg = <0x100 0x100>; + }; + }; + }; + +}; + +&dcc { + status = "okay"; +}; diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig new file mode 100644 index 000..7c7e143 --- /dev/null +++ b/configs/zynq_cse_nand_defconfig @@ -0,0 +1,50 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="zynq_cse" +CONFIG_ARCH_ZYNQ=y +CONFIG_SYS_TEXT_BASE=0x10 +CONFIG_SPL_STACK_R_ADDR=0x20 +CONFIG_SYS_MALLOC_LEN=0x2 +CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-nand" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL=y +CONFI
Re: [U-Boot] [PATCH 3/4] arm: zynq: Add Nand flash mini u-boot configuration for zynq
On 5.6.2018 09:21, Siva Durga Prasad Paladugu wrote: > Add configuration files/dtses for mini u-boot configuration > which runs on smaller footprint of memory. This configuration > has only required nand flash support. > > Signed-off-by: Siva Durga Prasad Paladugu > --- > arch/arm/dts/Makefile | 1 + > arch/arm/dts/zynq-cse-nand.dts | 90 > + > configs/zynq_cse_nand_defconfig | 50 +++ > 3 files changed, 141 insertions(+) > create mode 100644 arch/arm/dts/zynq-cse-nand.dts > create mode 100644 configs/zynq_cse_nand_defconfig > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile > index a0349a8..71b7c3a 100644 > --- a/arch/arm/dts/Makefile > +++ b/arch/arm/dts/Makefile > @@ -128,6 +128,7 @@ dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \ > > dtb-$(CONFIG_ARCH_ZYNQ) += \ > zynq-cc108.dtb \ > + zynq-cse-nand.dtb \ > zynq-cse-qspi-single.dtb \ > zynq-microzed.dtb \ > zynq-picozed.dtb \ > diff --git a/arch/arm/dts/zynq-cse-nand.dts b/arch/arm/dts/zynq-cse-nand.dts > new file mode 100644 > index 000..9df5f9a > --- /dev/null > +++ b/arch/arm/dts/zynq-cse-nand.dts > @@ -0,0 +1,90 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Xilinx CSE NAND board DTS > + * > + * Copyright (C) 2018 Xilinx, Inc. > + */ > +/dts-v1/; > + > +/ { > + #address-cells = <1>; > + #size-cells = <1>; > + model = "Zynq CSE NAND Board"; > + compatible = "xlnx,zynq-cse-nand", "xlnx,zynq-7000"; > + > + aliases { > + serial0 = &dcc; > + }; > + > + memory@fffc { this will be reported by latest DTC. This is > + device_type = "memory"; > + reg = <0x0 0x40>; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + dcc: dcc { > + compatible = "arm,dcc"; > + status = "disabled"; > + u-boot,dm-pre-reloc; > + }; > + > + amba: amba { > + u-boot,dm-pre-reloc; > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + interrupt-parent = <&intc>; > + ranges; > + > + intc: interrupt-controller@f8f01000 { > + compatible = "arm,cortex-a9-gic"; > + #interrupt-cells = <3>; > + interrupt-controller; > + reg = <0xF8F01000 0x1000>, > + <0xF8F00100 0x100>; > + }; we can save some space by removing this intc node too. > + > + slcr: slcr@f800 { > + u-boot,dm-pre-reloc; > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "xlnx,zynq-slcr", "syscon", "simple-bus"; > + reg = <0xF800 0x1000>; > + ranges; > + clkc: clkc@100 { > + u-boot,dm-pre-reloc; > + #clock-cells = <1>; > + compatible = "xlnx,ps7-clkc"; > + fclk-enable = <0xf>; we can remove this. > + clock-output-names = "armpll", "ddrpll", > + "iopll", "cpu_6or4x", > + "cpu_3or2x", "cpu_2x", "cpu_1x", > + "ddr2x", "ddr3x", "dci", > + "lqspi", "smc", "pcap", "gem0", > + "gem1", "fclk0", "fclk1", > + "fclk2", "fclk3", "can0", > + "can1", "sdio0", "sdio1", > + "uart0", "uart1", "spi0", > + "spi1", "dma", "usb0_aper", > + "usb1_aper", "gem0_aper", > + "gem1_aper", "sdio0_aper", > + "sdio1_aper", "spi0_aper", > + "spi1_aper", "can0_aper", > + "can1_aper", "i2c0_aper", > + "i2c1_aper", "uart0_aper", > + "uart1_aper", "gpio_aper", > + "lqspi_aper", "smc_aper", > + "swdt", "dbg_trc", "dbg_apb"; > + reg = <0x100 0x100>; > + }; > + }; > + }; > + > +}; > + > +&dcc { > + status = "okay"; > +}; > diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig > new file mode 100644 > index 000..7c7e143 > --- /dev/null > +++ b/configs/zynq_cse_nand_defc