Re: [U-Boot] [PATCH 3/4] powerpc/85xx:Update NOR code base to support debugger
Hi Wolfgang, On Wednesday 07 March 2012 05:35 PM, Wolfgang Denk wrote: Dear Prabhakar Kushwaha, In message4f56deb0.6060...@freescale.com you wrote: + _mas0 = MAS0_TLBSEL(1) | + MAS0_ESEL(CONFIG_DEBUGGER_TEMP_TLB); You are using an undocumented CONFIG_ option here. This CONFIG_ is defined as part of documentation patch sent in this series CONFIG_ options must be documented in the README. Sure +#if defined(CONFIG_E500_V1_V2) !defined(CONFIG_SYS_RAMBOOT) What if no such debug support is needed, and code size hurts? sure it will. I agree with you. But this piece of code overcome debug restriction of e500 and e500v2 cores and I think fixing restriction is a good way to go. What do we do to disable this code if no debug support is needed, and the code size is considered critical? i will put this piece of code under #if defined (CONFIG_DEBUGGER_TEMP_TLB). This piece of code will only be enabled when someone wants debugging here. And the requirement is temporary TLB. +#define CONFIG_DEBUGGER_TEMP_TLB 3 Undocumented! This CONFIG_ is defined as part of documentation patch sent in this series This is not sufficient, see above. i will add the description. Regards, Prabhakar ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/4] powerpc/85xx:Update NOR code base to support debugger
Dear Prabhakar Kushwaha, In message 4f56deb0.6060...@freescale.com you wrote: + _mas0 = MAS0_TLBSEL(1) | + MAS0_ESEL(CONFIG_DEBUGGER_TEMP_TLB); You are using an undocumented CONFIG_ option here. This CONFIG_ is defined as part of documentation patch sent in this series CONFIG_ options must be documented in the README. +#if defined(CONFIG_E500_V1_V2) !defined(CONFIG_SYS_RAMBOOT) What if no such debug support is needed, and code size hurts? sure it will. I agree with you. But this piece of code overcome debug restriction of e500 and e500v2 cores and I think fixing restriction is a good way to go. What do we do to disable this code if no debug support is needed, and the code size is considered critical? +#define CONFIG_DEBUGGER_TEMP_TLB 3 Undocumented! This CONFIG_ is defined as part of documentation patch sent in this series This is not sufficient, see above. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Virtue is a relative term. -- Spock, Friday's Child, stardate 3499.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/4] powerpc/85xx:Update NOR code base to support debugger
Dear Prabhakar Kushwaha, In message 1329296055-28541-1-git-send-email-prabha...@freescale.com you wrote: Update the NOR code base to support NOR-boot debugging. It ovecome e500 and e500v2's second limitation i.e. IVPR + IVOR15 should be valid fetchable OP code address. While executing in translated space (AS=1), whenever a debug exception is generated, the MSR[DS/IS] gets cleared and the processor tries to fetch an instruction from the debug exception vector (IVPR|IVOR15); since now we are in AS=0, the application needs to ensure the proper configuration to have IVOR|IVOR15 accessible from AS=0 also. Signed-off-by: Radu Lazarescu radu.lazare...@freescale.com Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com ... + _mas0 = MAS0_TLBSEL(1) | + MAS0_ESEL(CONFIG_DEBUGGER_TEMP_TLB); You are using an undocumented CONFIG_ option here. +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -184,6 +184,48 @@ l2_disabled: andi. r1,r3,L1CSR0_DCE@l beq 2b +#if defined(CONFIG_E500_V1_V2) !defined(CONFIG_SYS_RAMBOOT) What if no such debug support is needed, and code size hurts? @@ -107,6 +107,7 @@ #define CONFIG_MAX_CPUS 1 #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_DEBUGGER_TEMP_TLB 3 Undocumented! Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de If at first you don't succeed, you are running about average. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/4] powerpc/85xx:Update NOR code base to support debugger
Hi Wolfgang, On Tuesday 06 March 2012 08:15 PM, Wolfgang Denk wrote: Dear Prabhakar Kushwaha, In message1329296055-28541-1-git-send-email-prabha...@freescale.com you wrote: Update the NOR code base to support NOR-boot debugging. It ovecome e500 and e500v2's second limitation i.e. IVPR + IVOR15 should be valid fetchable OP code address. While executing in translated space (AS=1), whenever a debug exception is generated, the MSR[DS/IS] gets cleared and the processor tries to fetch an instruction from the debug exception vector (IVPR|IVOR15); since now we are in AS=0, the application needs to ensure the proper configuration to have IVOR|IVOR15 accessible from AS=0 also. Signed-off-by: Radu Lazarescuradu.lazare...@freescale.com Signed-off-by: Prabhakar Kushwahaprabha...@freescale.com ... + _mas0 = MAS0_TLBSEL(1) | + MAS0_ESEL(CONFIG_DEBUGGER_TEMP_TLB); You are using an undocumented CONFIG_ option here. This CONFIG_ is defined as part of documentation patch sent in this series +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -184,6 +184,48 @@ l2_disabled: andi. r1,r3,L1CSR0_DCE@l beq 2b +#if defined(CONFIG_E500_V1_V2) !defined(CONFIG_SYS_RAMBOOT) What if no such debug support is needed, and code size hurts? sure it will. I agree with you. But this piece of code overcome debug restriction of e500 and e500v2 cores and I think fixing restriction is a good way to go. @@ -107,6 +107,7 @@ #define CONFIG_MAX_CPUS 1 #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_DEBUGGER_TEMP_TLB 3 Undocumented! This CONFIG_ is defined as part of documentation patch sent in this series --Prabhakar ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/4] powerpc/85xx:Update NOR code base to support debugger
Update the NOR code base to support NOR-boot debugging. It ovecome e500 and e500v2's second limitation i.e. IVPR + IVOR15 should be valid fetchable OP code address. While executing in translated space (AS=1), whenever a debug exception is generated, the MSR[DS/IS] gets cleared and the processor tries to fetch an instruction from the debug exception vector (IVPR|IVOR15); since now we are in AS=0, the application needs to ensure the proper configuration to have IVOR|IVOR15 accessible from AS=0 also. Signed-off-by: Radu Lazarescu radu.lazare...@freescale.com Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com --- Applies on http://git.denx.de/u-boot.git branch master arch/powerpc/cpu/mpc85xx/cpu_init_early.c | 32 +- arch/powerpc/cpu/mpc85xx/start.S | 42 + arch/powerpc/include/asm/config_mpc85xx.h |3 +- 3 files changed, 75 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c index 091af7c..753f739 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c @@ -1,5 +1,5 @@ /* - * Copyright 2009-2011 Freescale Semiconductor, Inc + * Copyright 2009-2012 Freescale Semiconductor, Inc * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -53,6 +53,36 @@ void setup_ifc(void) asm volatile(isync;msync;tlbwe;isync); +#if defined(CONFIG_E500_V1_V2) +/* + * TLB for debuggging in AS1 + * Create temporary TLB in AS0 to handle debug exception + * As on debug exception MSR is cleared i.e. Address space is changed + * to 0. A TLB (in AS0) is required to handle debug exception generated + * in AS1. + * + * TLB is created for IVPR + IVOR15 to map on valid OP code address + * bacause flash's physical address is going to change as + * CONFIG_SYS_FLASH_BASE_PHYS. + */ + _mas0 = MAS0_TLBSEL(1) | + MAS0_ESEL(CONFIG_DEBUGGER_TEMP_TLB); + _mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_IPROT | + MAS1_TSIZE(BOOKE_PAGESZ_4M); + _mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G); + _mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX); + _mas7 = FSL_BOOKE_MAS7(flash_phys); + + mtspr(MAS0, _mas0); + mtspr(MAS1, _mas1); + mtspr(MAS2, _mas2); + mtspr(MAS3, _mas3); + mtspr(MAS7, _mas7); + + asm volatile(isync;msync;tlbwe;isync); +#endif + + /* Change flash's physical address */ out_be32((ifc_regs-cspr_cs[0].cspr), CONFIG_SYS_CSPR0); out_be32((ifc_regs-csor_cs[0].csor), CONFIG_SYS_CSOR0); out_be32((ifc_regs-amask_cs[0].amask), CONFIG_SYS_AMASK0); diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 09111e6..26c32df 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -184,6 +184,48 @@ l2_disabled: andi. r1,r3,L1CSR0_DCE@l beq 2b +#if defined(CONFIG_E500_V1_V2) !defined(CONFIG_SYS_RAMBOOT) +/* + * TLB for debuggging in AS1 + * Create temporary TLB in AS0 to handle debug exception + * As on debug exception MSR is cleared i.e. Address space is changed + * to 0. A TLB (in AS0) is required to handle debug exception generated + * in AS1. + * + * TLB is created for IVPR + IVOR15 to map on valid OP code address + * bacause flash's virtual address maps to 0xff80 - 0x. + * and this window is outside of 4K boot window. + */ + + lis r6,FSL_BOOKE_MAS0(1, + CONFIG_DEBUGGER_TEMP_TLB, 0)@h + ori r6,r6,FSL_BOOKE_MAS0(1, + CONFIG_DEBUGGER_TEMP_TLB, 0)@l + lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4M)@h + ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4M)@l + + lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE 0xffc0, + (MAS2_I|MAS2_G))@h + ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE 0xffc0, + (MAS2_I|MAS2_G))@l + + /* The 85xx has the default boot window 0xff80 - 0x */ + lis r9,FSL_BOOKE_MAS3(0xffc0, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r9,r9,FSL_BOOKE_MAS3(0xffc0, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l + + lis r10,0xffc0@h + ori r10,r10,0xffc0@l + + mtspr MAS0,r6 + mtspr MAS1,r7 + mtspr MAS2,r8 + mtspr MAS3,r9 + mtspr MAS7,r10 + isync + msync + tlbwe +#endif + /* * Ne need to setup interrupt vector for NAND SPL * because NAND SPL never compiles it. diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 8654625..cf97844 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++
