Re: [U-Boot] [PATCH 3/4 v2] x86: gpio: add pinctrl support from the device tree

2015-05-11 Thread gabriel huau 

Hi Simon,

Sorry for the delay, I'm gonna provide a new version in the next few 
days but here is some answers to your question:


On 04/28/2015 06:53 AM, Simon Glass wrote:

Hi Gabriel,

On 25 April 2015 at 14:17, Gabriel Huau cont...@huau-gabriel.fr wrote:

Every pin can be configured now from the device tree. A dt-bindings
has been added to describe the different property available.

Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
Changes for v2:
 - Clean commit message
 - Rename compatible string 'ich6' to 'x86'
 - Fix coding style
 - Create a dt-bindinds documentation
 - Move x86-gpio defines to a specific header
 - Reorder the functions to avoid the need for forward declarations
 - Rename double underscore functions to only one
 - Create a specific function to configure one pin
 - Use a define to prevent build/support issues with other x86 CPU that
 doesn't have a IOBASE.

I have a few minor comments below. Do you know how to access the GPIO
pings on the top connector of the Minnowboard MAX? I'd like to figure
out the pin names for those in U-Boot and that would allow me to test
a few things.


You should be able to access SOC_GPIO_S5_0, SOC_GPIO_S5_1, SOC_GPIO_S5_2

GPIO_BASE should be 0x80 (respecting bit 0 1 and 2).
IO_BASE should be 0x1D0, 0x210, 0x1E0 (respect GPIO0, 1 and 2).


  arch/x86/dts/minnowmax.dts |  21 ++
  arch/x86/include/asm/arch-baytrail/gpio.h  |   1 +
  arch/x86/include/asm/gpio.h|   1 +
  .../gpio/intel,x86-pinctrl.txt |  31 +++
  drivers/gpio/intel_ich6_gpio.c | 234 ++---
  include/dt-bindings/gpio/x86-gpio.h|  36 
  6 files changed, 295 insertions(+), 29 deletions(-)
  create mode 100644 doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
  create mode 100644 include/dt-bindings/gpio/x86-gpio.h

diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index c73e421..ea10963 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -6,6 +6,8 @@

  /dts-v1/;

+#include dt-bindings/gpio/x86-gpio.h
+
  /include/ skeleton.dtsi
  /include/ serial.dtsi

@@ -21,6 +23,25 @@
 silent_console = 0;
 };

+   pch_pinctrl {
+   compatible = intel,x86-pinctrl;
+   pin_usb_host_en0@0 {
+   gpio-offset = 0x80 8;
+   pad-offset = 0x260;
+   mode-gpio;
+   output-value = 1;
+   direction = PIN_OUTPUT;
+   };
+
+   pin_usb_host_en1@0 {
+   gpio-offset = 0x80 9;
+   pad-offset = 0x258;
+   mode-gpio;
+   output-value = 1;
+   direction = PIN_OUTPUT;
+   };
+   };
+
 gpioa {
 compatible = intel,ich6-gpio;
 u-boot,dm-pre-reloc;
diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h 
b/arch/x86/include/asm/arch-baytrail/gpio.h
index 4e8987c..85a65a8 100644
--- a/arch/x86/include/asm/arch-baytrail/gpio.h
+++ b/arch/x86/include/asm/arch-baytrail/gpio.h
@@ -9,5 +9,6 @@

  /* Where in config space is the register that points to the GPIO registers? */
  #define PCI_CFG_GPIOBASE 0x48
+#define PCI_CFG_IOBASE   0x4c

Can we put this in the device tree as a property of the pch_pinctrl
node? If you like we could do it later.
Yes, I will do the modification, I thought as a first version it would 
be easier to use a define but actually, a property is cleaner and also 
easy to implement.



  #endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
index 1099427..ed85b08 100644
--- a/arch/x86/include/asm/gpio.h
+++ b/arch/x86/include/asm/gpio.h
@@ -147,6 +147,7 @@ struct pch_gpio_map {
 } set3;
  };

+int gpio_ich6_pinctrl_init(void);
  void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio);
  void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);

diff --git a/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt 
b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
new file mode 100644
index 000..45ab1af
--- /dev/null
+++ b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
@@ -0,0 +1,31 @@
+Intel x86 PINCTRL/GPIO controller
+
+Pin-muxing on x86 can be described with a node for the PINCTRL master
+node and a set of child nodes for each pin on the SoC.
+
+The PINCTRL master node requires the following properties:
+- compatible : intel,x86-pinctrl
+
+Pin nodes must be children of the pinctrl master node and can
+contain the following properties:
+- pad-offset- (required) offset in the IOBASE for the pin to 
configured.
+- gpio-offset   - (required) offset in the GPIOBASE for the pin to 
configured and
+   also the bit

Re: [U-Boot] [PATCH 3/4 v2] x86: gpio: add pinctrl support from the device tree

2015-05-11 Thread gabriel huau 

Hi Stephen,

Thanks for the feedback, I completely miss it, I will do the 
modification for the v3.


On 04/28/2015 08:22 AM, Stephen Warren wrote:

On 04/28/2015 07:53 AM, Simon Glass wrote:

Hi Gabriel,

On 25 April 2015 at 14:17, Gabriel Huau cont...@huau-gabriel.fr wrote:

Every pin can be configured now from the device tree. A dt-bindings
has been added to describe the different property available.


diff --git a/include/dt-bindings/gpio/x86-gpio.h 
b/include/dt-bindings/gpio/x86-gpio.h



+/*
+ * This header provides constants for binding nvidia,tegra*-gpio.
+ *
+ * The first cell in Tegra's GPIO specifier is the GPIO ID. The 
macros below

+ * provide names for this.


I think this comment needs updating.


Regards,
Gabriel

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Re: [U-Boot] [PATCH 3/4 v2] x86: gpio: add pinctrl support from the device tree

2015-04-28 Thread Simon Glass 
Hi Gabriel,

On 25 April 2015 at 14:17, Gabriel Huau cont...@huau-gabriel.fr wrote:
 Every pin can be configured now from the device tree. A dt-bindings
 has been added to describe the different property available.

 Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
 ---
 Changes for v2:
 - Clean commit message
 - Rename compatible string 'ich6' to 'x86'
 - Fix coding style
 - Create a dt-bindinds documentation
 - Move x86-gpio defines to a specific header
 - Reorder the functions to avoid the need for forward declarations
 - Rename double underscore functions to only one
 - Create a specific function to configure one pin
 - Use a define to prevent build/support issues with other x86 CPU that
 doesn't have a IOBASE.

I have a few minor comments below. Do you know how to access the GPIO
pings on the top connector of the Minnowboard MAX? I'd like to figure
out the pin names for those in U-Boot and that would allow me to test
a few things.


  arch/x86/dts/minnowmax.dts |  21 ++
  arch/x86/include/asm/arch-baytrail/gpio.h  |   1 +
  arch/x86/include/asm/gpio.h|   1 +
  .../gpio/intel,x86-pinctrl.txt |  31 +++
  drivers/gpio/intel_ich6_gpio.c | 234 
 ++---
  include/dt-bindings/gpio/x86-gpio.h|  36 
  6 files changed, 295 insertions(+), 29 deletions(-)
  create mode 100644 doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
  create mode 100644 include/dt-bindings/gpio/x86-gpio.h

 diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
 index c73e421..ea10963 100644
 --- a/arch/x86/dts/minnowmax.dts
 +++ b/arch/x86/dts/minnowmax.dts
 @@ -6,6 +6,8 @@

  /dts-v1/;

 +#include dt-bindings/gpio/x86-gpio.h
 +
  /include/ skeleton.dtsi
  /include/ serial.dtsi

 @@ -21,6 +23,25 @@
 silent_console = 0;
 };

 +   pch_pinctrl {
 +   compatible = intel,x86-pinctrl;
 +   pin_usb_host_en0@0 {
 +   gpio-offset = 0x80 8;
 +   pad-offset = 0x260;
 +   mode-gpio;
 +   output-value = 1;
 +   direction = PIN_OUTPUT;
 +   };
 +
 +   pin_usb_host_en1@0 {
 +   gpio-offset = 0x80 9;
 +   pad-offset = 0x258;
 +   mode-gpio;
 +   output-value = 1;
 +   direction = PIN_OUTPUT;
 +   };
 +   };
 +
 gpioa {
 compatible = intel,ich6-gpio;
 u-boot,dm-pre-reloc;
 diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h 
 b/arch/x86/include/asm/arch-baytrail/gpio.h
 index 4e8987c..85a65a8 100644
 --- a/arch/x86/include/asm/arch-baytrail/gpio.h
 +++ b/arch/x86/include/asm/arch-baytrail/gpio.h
 @@ -9,5 +9,6 @@

  /* Where in config space is the register that points to the GPIO registers? 
 */
  #define PCI_CFG_GPIOBASE 0x48
 +#define PCI_CFG_IOBASE   0x4c

Can we put this in the device tree as a property of the pch_pinctrl
node? If you like we could do it later.


  #endif /* _X86_ARCH_GPIO_H_ */
 diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
 index 1099427..ed85b08 100644
 --- a/arch/x86/include/asm/gpio.h
 +++ b/arch/x86/include/asm/gpio.h
 @@ -147,6 +147,7 @@ struct pch_gpio_map {
 } set3;
  };

 +int gpio_ich6_pinctrl_init(void);
  void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio);
  void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);

 diff --git a/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt 
 b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
 new file mode 100644
 index 000..45ab1af
 --- /dev/null
 +++ b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
 @@ -0,0 +1,31 @@
 +Intel x86 PINCTRL/GPIO controller
 +
 +Pin-muxing on x86 can be described with a node for the PINCTRL master
 +node and a set of child nodes for each pin on the SoC.
 +
 +The PINCTRL master node requires the following properties:
 +- compatible : intel,x86-pinctrl
 +
 +Pin nodes must be children of the pinctrl master node and can
 +contain the following properties:
 +- pad-offset- (required) offset in the IOBASE for the pin to 
 configured.
 +- gpio-offset   - (required) offset in the GPIOBASE for the pin to 
 configured and
 +   also the bit shift in this register.
 +- mode-gpio- (optional) standalone property to force the 
 pin into GPIO mode.
 +- mode-func- (optional) function number to assign to the 
 pin. if 'mode-gpio'
 +   is set, this property will be ignored.
 +in case of 'mode-gpio' property set:
 +- output-value - (optional) this set the default output value of the 
 GPIO.
 +- direction -

Re: [U-Boot] [PATCH 3/4 v2] x86: gpio: add pinctrl support from the device tree

2015-04-28 Thread Stephen Warren 

On 04/28/2015 07:53 AM, Simon Glass wrote:

Hi Gabriel,

On 25 April 2015 at 14:17, Gabriel Huau cont...@huau-gabriel.fr wrote:

Every pin can be configured now from the device tree. A dt-bindings
has been added to describe the different property available.



diff --git a/include/dt-bindings/gpio/x86-gpio.h 
b/include/dt-bindings/gpio/x86-gpio.h



+/*
+ * This header provides constants for binding nvidia,tegra*-gpio.
+ *
+ * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
+ * provide names for this.


I think this comment needs updating.
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[U-Boot] [PATCH 3/4 v2] x86: gpio: add pinctrl support from the device tree

2015-04-25 Thread Gabriel Huau 
Every pin can be configured now from the device tree. A dt-bindings
has been added to describe the different property available.

Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
Changes for v2:
- Clean commit message
- Rename compatible string 'ich6' to 'x86'
- Fix coding style
- Create a dt-bindinds documentation
- Move x86-gpio defines to a specific header
- Reorder the functions to avoid the need for forward declarations
- Rename double underscore functions to only one
- Create a specific function to configure one pin
- Use a define to prevent build/support issues with other x86 CPU that
doesn't have a IOBASE.

 arch/x86/dts/minnowmax.dts |  21 ++
 arch/x86/include/asm/arch-baytrail/gpio.h  |   1 +
 arch/x86/include/asm/gpio.h|   1 +
 .../gpio/intel,x86-pinctrl.txt |  31 +++
 drivers/gpio/intel_ich6_gpio.c | 234 ++---
 include/dt-bindings/gpio/x86-gpio.h|  36 
 6 files changed, 295 insertions(+), 29 deletions(-)
 create mode 100644 doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
 create mode 100644 include/dt-bindings/gpio/x86-gpio.h

diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index c73e421..ea10963 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -6,6 +6,8 @@
 
 /dts-v1/;
 
+#include dt-bindings/gpio/x86-gpio.h
+
 /include/ skeleton.dtsi
 /include/ serial.dtsi
 
@@ -21,6 +23,25 @@
silent_console = 0;
};
 
+   pch_pinctrl {
+   compatible = intel,x86-pinctrl;
+   pin_usb_host_en0@0 {
+   gpio-offset = 0x80 8;
+   pad-offset = 0x260;
+   mode-gpio;
+   output-value = 1;
+   direction = PIN_OUTPUT;
+   };
+
+   pin_usb_host_en1@0 {
+   gpio-offset = 0x80 9;
+   pad-offset = 0x258;
+   mode-gpio;
+   output-value = 1;
+   direction = PIN_OUTPUT;
+   };
+   };
+
gpioa {
compatible = intel,ich6-gpio;
u-boot,dm-pre-reloc;
diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h 
b/arch/x86/include/asm/arch-baytrail/gpio.h
index 4e8987c..85a65a8 100644
--- a/arch/x86/include/asm/arch-baytrail/gpio.h
+++ b/arch/x86/include/asm/arch-baytrail/gpio.h
@@ -9,5 +9,6 @@
 
 /* Where in config space is the register that points to the GPIO registers? */
 #define PCI_CFG_GPIOBASE 0x48
+#define PCI_CFG_IOBASE   0x4c
 
 #endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
index 1099427..ed85b08 100644
--- a/arch/x86/include/asm/gpio.h
+++ b/arch/x86/include/asm/gpio.h
@@ -147,6 +147,7 @@ struct pch_gpio_map {
} set3;
 };
 
+int gpio_ich6_pinctrl_init(void);
 void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio);
 void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
 
diff --git a/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt 
b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
new file mode 100644
index 000..45ab1af
--- /dev/null
+++ b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
@@ -0,0 +1,31 @@
+Intel x86 PINCTRL/GPIO controller
+
+Pin-muxing on x86 can be described with a node for the PINCTRL master
+node and a set of child nodes for each pin on the SoC.
+
+The PINCTRL master node requires the following properties:
+- compatible : intel,x86-pinctrl
+
+Pin nodes must be children of the pinctrl master node and can
+contain the following properties:
+- pad-offset- (required) offset in the IOBASE for the pin to 
configured.
+- gpio-offset   - (required) offset in the GPIOBASE for the pin to 
configured and
+   also the bit shift in this register.
+- mode-gpio- (optional) standalone property to force the 
pin into GPIO mode.
+- mode-func- (optional) function number to assign to the 
pin. if 'mode-gpio'
+   is set, this property will be ignored.
+in case of 'mode-gpio' property set:
+- output-value - (optional) this set the default output value of the 
GPIO.
+- direction - (optional) this set the direction of the gpio.
+- pull-str  - (optional) this set the pull strength of the pin.
+- pull-assign   - (optional) this set the pull assignement (up/down) of 
the pin.
+
+Example:
+
+pin_usb_host_en0@0 {
+gpio-offset = 0x80 8;
+pad-offset = 0x260;
+mode-gpio;
+output-value = 1;
+direction = PIN_OUTPUT;
+};
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index 7e679a0..c18c60f 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++