This test is built on top of the existing swap_case driver. It adds EA
capability structure support to swap_case and uses that to map BARs.
BAR1 works as it used to, swapping upper/lower case. BARs 2,4 map to a
couple of magic values.
Signed-off-by: Alex Marginean
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
Changes in v2:
- new patch, v1 didn't have a test
Changes in v3:
- renamed sandbox_swap_use_ea function for consistency
- fixed several typos and styling issues
arch/sandbox/dts/test.dts | 8 +++
arch/sandbox/include/asm/test.h | 13
drivers/misc/swap_case.c| 102 +++-
test/dm/pci.c | 49 +++
4 files changed, 171 insertions(+), 1 deletion(-)
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 46d8a56d0f..dd50a951a8 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -434,6 +434,14 @@
compatible = "sandbox,swap-case";
};
};
+ pci@1,0 {
+ compatible = "pci-generic";
+ reg = <0x0800 0 0 0 0>;
+ emul@0,0 {
+ compatible = "sandbox,swap-case";
+ use-ea;
+ };
+ };
pci@1f,0 {
compatible = "pci-generic";
reg = <0xf800 0 0 0 0>;
diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h
index e956a05262..32125f3037 100644
--- a/arch/sandbox/include/asm/test.h
+++ b/arch/sandbox/include/asm/test.h
@@ -19,6 +19,7 @@
#define PCI_CAP_ID_PM_OFFSET 0x50
#define PCI_CAP_ID_EXP_OFFSET 0x60
#define PCI_CAP_ID_MSIX_OFFSET 0x70
+#define PCI_CAP_ID_EA_OFFSET 0x80
#define PCI_EXT_CAP_ID_ERR_OFFSET 0x100
#define PCI_EXT_CAP_ID_VC_OFFSET 0x200
@@ -30,6 +31,18 @@
#define SANDBOX_CLK_RATE 32768
+/* Macros used to test PCI EA capability structure */
+#define PCI_CAP_EA_BASE_LO00x0010
+#define PCI_CAP_EA_BASE_LO10x0011
+#define PCI_CAP_EA_BASE_LO20x0012
+#define PCI_CAP_EA_BASE_LO40x0014
+#define PCI_CAP_EA_BASE_HI20x0002ULL
+#define PCI_CAP_EA_BASE_HI40x0004ULL
+#define PCI_CAP_EA_SIZE_LO 0x
+#define PCI_CAP_EA_SIZE_HI 0x0010ULL
+#define PCI_EA_BAR2_MAGIC 0x72727272
+#define PCI_EA_BAR4_MAGIC 0x74747474
+
/* System controller driver data */
enum {
SYSCON0 = 32,
diff --git a/drivers/misc/swap_case.c b/drivers/misc/swap_case.c
index fa608cec1b..6afc6d9466 100644
--- a/drivers/misc/swap_case.c
+++ b/drivers/misc/swap_case.c
@@ -61,11 +61,63 @@ static int sandbox_swap_case_get_devfn(struct udevice *dev)
return plat->devfn;
}
+static int sandbox_swap_case_use_ea(struct udevice *dev)
+{
+ return !!ofnode_get_property(dev->node, "use-ea", NULL);
+}
+
+/* Please keep these macros in sync with ea_regs below */
+#define PCI_CAP_ID_EA_SIZE (sizeof(ea_regs) + 4)
+#define PCI_CAP_ID_EA_ENTRY_CNT4
+/* Hardcoded EA structure, excluding 1st DW. */
+static const u32 ea_regs[] = {
+ /* BEI=0, ES=2, BAR0 32b Base + 32b MaxOffset, I/O space */
+ (2 << 8) | 2,
+ PCI_CAP_EA_BASE_LO0,
+ 0,
+ /* BEI=1, ES=2, BAR1 32b Base + 32b MaxOffset */
+ (1 << 4) | 2,
+ PCI_CAP_EA_BASE_LO1,
+ MEM_TEXT_SIZE - 1,
+ /* BEI=2, ES=3, BAR2 64b Base + 32b MaxOffset */
+ (2 << 4) | 3,
+ PCI_CAP_EA_BASE_LO2 | PCI_EA_IS_64,
+ PCI_CAP_EA_SIZE_LO,
+ PCI_CAP_EA_BASE_HI2,
+ /* BEI=4, ES=4, BAR4 64b Base + 64b MaxOffset */
+ (4 << 4) | 4,
+ PCI_CAP_EA_BASE_LO4 | PCI_EA_IS_64,
+ PCI_CAP_EA_SIZE_LO | PCI_EA_IS_64,
+ PCI_CAP_EA_BASE_HI4,
+ PCI_CAP_EA_SIZE_HI,
+};
+
+static int sandbox_swap_case_read_ea(struct udevice *emul, uint offset,
+ulong *valuep, enum pci_size_t size)
+{
+ u32 reg;
+
+ offset = offset - PCI_CAP_ID_EA_OFFSET - 4;
+ reg = ea_regs[offset >> 2];
+ reg >>= (offset % 4) * 8;
+
+ *valuep = reg;
+ return 0;
+}
+
static int sandbox_swap_case_read_config(struct udevice *emul, uint offset,
ulong *valuep, enum pci_size_t size)
{
struct swap_case_platdata *plat = dev_get_platdata(emul);
+ /*
+* The content of the EA capability structure is handled elsewhere to
+* keep the switch/case below sane
+*/
+ if (offset > PCI_CAP_ID_EA_OFFSET + PCI_CAP_LIST_NEXT &&
+ offset < PCI_CAP_ID_EA_OFFSET + PCI_CAP_ID_EA_SIZE)
+ return sandbox_swap_case_read_ea(emul, offset, valuep, size);
+
switch (offset) {
c
