Re: [U-Boot] [PATCH 39/39] x86: ivybridge: Implement SDRAM init
Hi Simon, On Tue, Nov 11, 2014 at 8:29 AM, Simon Glass s...@chromium.org wrote: Hi Bin, On 9 November 2014 23:49, Bin Meng bmeng...@gmail.com wrote: Hi Simon, On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote: Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in the board directory and the SDRAM SPD information in the device tree. This also needs the Intel Management Engine (me.bin) to work. Binary blobs everywhere: so far we have MRC, ME and microcode. [snip] diff --git a/Makefile b/Makefile index 86d0510..4f0260f 100644 --- a/Makefile +++ b/Makefile @@ -956,9 +956,14 @@ u-boot.rom: u-boot-x86-16bit.bin u-boot-dtb.bin \ $(srctree)/board/$(BOARDDIR)/descriptor.bin $(objtree)/tools/ifdtool -c -r $(CONFIG_ROM_SIZE) \ -D $(srctree)/board/$(BOARDDIR)/descriptor.bin u-boot.tmp + $(objtree)/tools/ifdtool \ + -i ME:$(srctree)/board/$(BOARDDIR)/me.bin u-boot.tmp Can we make the ME injection depend on something like CONFIG_X86_HAVE_ME? Sure - do you have a case that doesn't use ME? The platform (Atom E6xx and EG20T) I am working on does not have the ME. Note it also does not have the descriptor.bin. Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 39/39] x86: ivybridge: Implement SDRAM init
Hi Bin, On 9 November 2014 23:49, Bin Meng bmeng...@gmail.com wrote: Hi Simon, On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote: Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in the board directory and the SDRAM SPD information in the device tree. This also needs the Intel Management Engine (me.bin) to work. Binary blobs everywhere: so far we have MRC, ME and microcode. [snip] diff --git a/Makefile b/Makefile index 86d0510..4f0260f 100644 --- a/Makefile +++ b/Makefile @@ -956,9 +956,14 @@ u-boot.rom: u-boot-x86-16bit.bin u-boot-dtb.bin \ $(srctree)/board/$(BOARDDIR)/descriptor.bin $(objtree)/tools/ifdtool -c -r $(CONFIG_ROM_SIZE) \ -D $(srctree)/board/$(BOARDDIR)/descriptor.bin u-boot.tmp + $(objtree)/tools/ifdtool \ + -i ME:$(srctree)/board/$(BOARDDIR)/me.bin u-boot.tmp Can we make the ME injection depend on something like CONFIG_X86_HAVE_ME? Sure - do you have a case that doesn't use ME? $(objtree)/tools/ifdtool -w \ $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot-dtb.bin u-boot.tmp $(objtree)/tools/ifdtool -w \ + $(CONFIG_X86_MRC_START):$(srctree)/board/$(BOARDDIR)/mrc.bin \ + u-boot.tmp Ditto. + $(objtree)/tools/ifdtool -w \ $(CONFIG_SYS_X86_START16):$(objtree)/u-boot-x86-16bit.bin \ u-boot.tmp mv u-boot.tmp $@ Regards, Bin Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 39/39] x86: ivybridge: Implement SDRAM init
Hi Simon, On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote: Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in the board directory and the SDRAM SPD information in the device tree. This also needs the Intel Management Engine (me.bin) to work. Binary blobs everywhere: so far we have MRC, ME and microcode. SDRAM init works by setting up various parameters and calling the MRC. This in turn does some sort of magic to work out how much memory there is and the timing parameters to use. It also sets up the DRAM controllers. When the MRC returns, we use the information it provides to map out the available memory in U-Boot. U-Boot normally moves itself to the top of RAM. On x86 the RAM is not generally contiguous, and anyway some RAM may be above 4GB which doesn't work in 32-bit mode. So we relocate to the top of the largest block of RAM we can find below 4GB. Memory above 4GB is accessible with special functions (see physmem). It would be possible to build U-Boot in 64-bit mode but this wouldn't necessarily provide any more memory, since the largest block is often below 4GB. Anyway U-Boot doesn't need huge amounts of memory - even a very large ramdisk seldom exceeds 100-200MB. U-Boot has support for booting 64-bit kernels directly so this does not pose a limitation in that area. Also there are probably parts of U-Boot that will not work correctly in 64-bit mode. The MRC is one. There is some work remaining in this area. Since memory init is very slow (over 500ms) it is possible to save the parameters in SPI flash to speed it up next time. Suspend/resume support is not fully implemented, or at least it is not efficient. With this patch, link boots to a prompt. Signed-off-by: Simon Glass s...@chromium.org --- Makefile | 5 + arch/x86/Kconfig | 11 + arch/x86/cpu/ivybridge/Makefile | 3 + arch/x86/cpu/ivybridge/early_me.c | 191 arch/x86/cpu/ivybridge/me_status.c| 195 arch/x86/cpu/ivybridge/report_platform.c | 98 arch/x86/cpu/ivybridge/sdram.c| 553 +- arch/x86/cpu/start.S | 10 +- arch/x86/dts/link.dts | 111 + arch/x86/include/asm/arch-ivybridge/me.h | 357 ++ arch/x86/include/asm/arch-ivybridge/pch.h | 113 + arch/x86/include/asm/arch-ivybridge/pei_data.h| 121 + arch/x86/include/asm/arch-ivybridge/sandybridge.h | 2 + arch/x86/include/asm/config.h | 1 + arch/x86/include/asm/global_data.h| 13 + arch/x86/include/asm/post.h | 5 + arch/x86/include/asm/u-boot-x86.h | 2 + arch/x86/lib/Makefile | 1 + arch/x86/lib/ramtest.c| 79 include/configs/chromebook_link.h | 5 + include/configs/x86-common.h | 2 +- include/fdtdec.h | 1 + lib/fdtdec.c | 1 + 23 files changed, 1874 insertions(+), 6 deletions(-) create mode 100644 arch/x86/cpu/ivybridge/early_me.c create mode 100644 arch/x86/cpu/ivybridge/me_status.c create mode 100644 arch/x86/cpu/ivybridge/report_platform.c create mode 100644 arch/x86/include/asm/arch-ivybridge/me.h create mode 100644 arch/x86/include/asm/arch-ivybridge/pei_data.h create mode 100644 arch/x86/lib/ramtest.c diff --git a/Makefile b/Makefile index 86d0510..4f0260f 100644 --- a/Makefile +++ b/Makefile @@ -956,9 +956,14 @@ u-boot.rom: u-boot-x86-16bit.bin u-boot-dtb.bin \ $(srctree)/board/$(BOARDDIR)/descriptor.bin $(objtree)/tools/ifdtool -c -r $(CONFIG_ROM_SIZE) \ -D $(srctree)/board/$(BOARDDIR)/descriptor.bin u-boot.tmp + $(objtree)/tools/ifdtool \ + -i ME:$(srctree)/board/$(BOARDDIR)/me.bin u-boot.tmp $(objtree)/tools/ifdtool -w \ $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot-dtb.bin u-boot.tmp $(objtree)/tools/ifdtool -w \ + $(CONFIG_X86_MRC_START):$(srctree)/board/$(BOARDDIR)/mrc.bin \ + u-boot.tmp + $(objtree)/tools/ifdtool -w \ $(CONFIG_SYS_X86_START16):$(objtree)/u-boot-x86-16bit.bin \ u-boot.tmp mv u-boot.tmp $@ diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 73fe8b2..e992610 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -50,6 +50,17 @@ config CPU_ADDR_BITS int default 36 +config HPET_ADDRESS + hex + default 0xfed0 if !HPET_ADDRESS_OVERRIDE + +config SMM_TSEG + bool + default n + +config SMM_TSEG_SIZE + hex + config ROM_SIZE hex
Re: [U-Boot] [PATCH 39/39] x86: ivybridge: Implement SDRAM init
Hi Simon, On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote: Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in the board directory and the SDRAM SPD information in the device tree. This also needs the Intel Management Engine (me.bin) to work. Binary blobs everywhere: so far we have MRC, ME and microcode. [snip] diff --git a/Makefile b/Makefile index 86d0510..4f0260f 100644 --- a/Makefile +++ b/Makefile @@ -956,9 +956,14 @@ u-boot.rom: u-boot-x86-16bit.bin u-boot-dtb.bin \ $(srctree)/board/$(BOARDDIR)/descriptor.bin $(objtree)/tools/ifdtool -c -r $(CONFIG_ROM_SIZE) \ -D $(srctree)/board/$(BOARDDIR)/descriptor.bin u-boot.tmp + $(objtree)/tools/ifdtool \ + -i ME:$(srctree)/board/$(BOARDDIR)/me.bin u-boot.tmp Can we make the ME injection depend on something like CONFIG_X86_HAVE_ME? $(objtree)/tools/ifdtool -w \ $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot-dtb.bin u-boot.tmp $(objtree)/tools/ifdtool -w \ + $(CONFIG_X86_MRC_START):$(srctree)/board/$(BOARDDIR)/mrc.bin \ + u-boot.tmp Ditto. + $(objtree)/tools/ifdtool -w \ $(CONFIG_SYS_X86_START16):$(objtree)/u-boot-x86-16bit.bin \ u-boot.tmp mv u-boot.tmp $@ Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 39/39] x86: ivybridge: Implement SDRAM init
Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in the board directory and the SDRAM SPD information in the device tree. This also needs the Intel Management Engine (me.bin) to work. Binary blobs everywhere: so far we have MRC, ME and microcode. SDRAM init works by setting up various parameters and calling the MRC. This in turn does some sort of magic to work out how much memory there is and the timing parameters to use. It also sets up the DRAM controllers. When the MRC returns, we use the information it provides to map out the available memory in U-Boot. U-Boot normally moves itself to the top of RAM. On x86 the RAM is not generally contiguous, and anyway some RAM may be above 4GB which doesn't work in 32-bit mode. So we relocate to the top of the largest block of RAM we can find below 4GB. Memory above 4GB is accessible with special functions (see physmem). It would be possible to build U-Boot in 64-bit mode but this wouldn't necessarily provide any more memory, since the largest block is often below 4GB. Anyway U-Boot doesn't need huge amounts of memory - even a very large ramdisk seldom exceeds 100-200MB. U-Boot has support for booting 64-bit kernels directly so this does not pose a limitation in that area. Also there are probably parts of U-Boot that will not work correctly in 64-bit mode. The MRC is one. There is some work remaining in this area. Since memory init is very slow (over 500ms) it is possible to save the parameters in SPI flash to speed it up next time. Suspend/resume support is not fully implemented, or at least it is not efficient. With this patch, link boots to a prompt. Signed-off-by: Simon Glass s...@chromium.org --- Makefile | 5 + arch/x86/Kconfig | 11 + arch/x86/cpu/ivybridge/Makefile | 3 + arch/x86/cpu/ivybridge/early_me.c | 191 arch/x86/cpu/ivybridge/me_status.c| 195 arch/x86/cpu/ivybridge/report_platform.c | 98 arch/x86/cpu/ivybridge/sdram.c| 553 +- arch/x86/cpu/start.S | 10 +- arch/x86/dts/link.dts | 111 + arch/x86/include/asm/arch-ivybridge/me.h | 357 ++ arch/x86/include/asm/arch-ivybridge/pch.h | 113 + arch/x86/include/asm/arch-ivybridge/pei_data.h| 121 + arch/x86/include/asm/arch-ivybridge/sandybridge.h | 2 + arch/x86/include/asm/config.h | 1 + arch/x86/include/asm/global_data.h| 13 + arch/x86/include/asm/post.h | 5 + arch/x86/include/asm/u-boot-x86.h | 2 + arch/x86/lib/Makefile | 1 + arch/x86/lib/ramtest.c| 79 include/configs/chromebook_link.h | 5 + include/configs/x86-common.h | 2 +- include/fdtdec.h | 1 + lib/fdtdec.c | 1 + 23 files changed, 1874 insertions(+), 6 deletions(-) create mode 100644 arch/x86/cpu/ivybridge/early_me.c create mode 100644 arch/x86/cpu/ivybridge/me_status.c create mode 100644 arch/x86/cpu/ivybridge/report_platform.c create mode 100644 arch/x86/include/asm/arch-ivybridge/me.h create mode 100644 arch/x86/include/asm/arch-ivybridge/pei_data.h create mode 100644 arch/x86/lib/ramtest.c diff --git a/Makefile b/Makefile index 86d0510..4f0260f 100644 --- a/Makefile +++ b/Makefile @@ -956,9 +956,14 @@ u-boot.rom: u-boot-x86-16bit.bin u-boot-dtb.bin \ $(srctree)/board/$(BOARDDIR)/descriptor.bin $(objtree)/tools/ifdtool -c -r $(CONFIG_ROM_SIZE) \ -D $(srctree)/board/$(BOARDDIR)/descriptor.bin u-boot.tmp + $(objtree)/tools/ifdtool \ + -i ME:$(srctree)/board/$(BOARDDIR)/me.bin u-boot.tmp $(objtree)/tools/ifdtool -w \ $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot-dtb.bin u-boot.tmp $(objtree)/tools/ifdtool -w \ + $(CONFIG_X86_MRC_START):$(srctree)/board/$(BOARDDIR)/mrc.bin \ + u-boot.tmp + $(objtree)/tools/ifdtool -w \ $(CONFIG_SYS_X86_START16):$(objtree)/u-boot-x86-16bit.bin \ u-boot.tmp mv u-boot.tmp $@ diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 73fe8b2..e992610 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -50,6 +50,17 @@ config CPU_ADDR_BITS int default 36 +config HPET_ADDRESS + hex + default 0xfed0 if !HPET_ADDRESS_OVERRIDE + +config SMM_TSEG + bool + default n + +config SMM_TSEG_SIZE + hex + config ROM_SIZE hex default 0x80 diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index 4bfb03a..6669a6f 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++
