Re: [U-Boot] [PATCH 4/4] powerpc/p4080: Add support for the P4080DS board
Hi Kumar,
That's great to see official 4080 board support! I had a few comments
below. I haven't dug into the 4080 much, so take them with a grain of
salt.
snip
+#ifdef CONFIG_PHYS_64BIT
+ puts(36-bit Addressing\n);
+#endif
Any chance CONFIG_ENABLE_36BIT_PHYS could be defined without
CONFIG_PHYS_64BIT, or vice-versa? Or any reason to not use
CONFIG_ENABLE_36BIT_PHYS above?
+ /* Display the actual SERDES reference clocks as configured by the
+ * dip switches on the board. Note that the SWx registers could
+ * technically be set to force the reference clocks to match the
+ * values that the SERDES expects (or vice versa). For now, however,
+ * we just display both values and hope the user notices when they
+ * don't match.
+ */
+ puts(SERDES Reference Clocks: );
+ sw = in_8(PIXIS_SW(3));
+ printf(Bank1=%uMHz , (sw 0x40) ? 125 : 100);
+ printf(Bank2=%sMHz , (sw 0x20) ? 156.25 : 125);
+ printf(Bank3=%sMHz\n, (sw 0x10) ? 156.25 : 125);
Could you use serdes_clock_to_string() above? It'd make the values
above a little less magical and be portable to other boards that don't
use the PIXIS FPGA.
+
+#ifdef CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+ /*
+ * Poll until memory is initialized. 512 Meg at 400MHz might hit this
+ * 200 times or so.
+ */
+ while ((ddr-sdram_cfg_2 16) != 0) {
+ debug(sdram_cfg2 = 0x%08x\n, ddr-sdram_cfg_2);
+ udelay(1000);
+ }
+ asm(sync; isync);
+ udelay(500);
+
+ while ((ddr2-sdram_cfg_2 16) != 0) {
+ debug(sdram_cfg2 = 0x%08x\n, ddr2-sdram_cfg_2);
+ udelay(1000);
+ }
+ asm(sync; isync);
+ udelay(500);
+#endif
Use in_be32()'s above? And change 16 to 0x10, or add a D_INIT define?
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size;
+
+ puts(Initializing\n);
+
+#ifdef CONFIG_DDR_SPD
+ dram_size = fsl_ddr_sdram();
+#else
+ dram_size = fixed_sdram();
+#endif
+ setup_ddr_tlbs(dram_size / 0x10);
+
+ puts(DDR: );
+ return dram_size;
+}
Should the puts(DDR:) be removed? With it I'd think the output would
be DRAM: DDR: (DDR3, 64-bit...). Ie the DDR is a bit redundant
and the spaces a bit excessive.
+#ifdef CONFIG_MP
+void board_lmb_reserve(struct lmb *lmb)
+{
+ cpu_mp_lmb_reserve(lmb);
+}
+#endif
It'd be nice to move the board_lmb_reserve() somewhere common at some
point since every board that has CONFIG_MP defined currently uses the
same chunk of code. Or maybe remove board_lmb_reserve() and have its
callees call cpu_mp_lmb_reserve().
+#include common.h
+#include asm/mmu.h
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+ SET_TLB_ENTRY(1, 0xf000, 0xf000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_16M, 1),
+
+ /* *I*G* - Flash, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x4000,
CONFIG_SYS_PCIE1_MEM_PHYS + 0x4000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT +
[U-Boot] [PATCH 4/4] powerpc/p4080: Add support for the P4080DS board
Add support for the P4080DS board, with the following features: * 36-bit only * Boots from NOR flash * FMAN drivers NOT supported * SPD fixed sdram DDR Signed-off-by: Ed Swarthout ed.swarth...@freescale.com Signed-off-by: Emil Medve emilian.me...@freescale.com Signed-off-by: Becky Bruce bec...@kernel.crashing.org Signed-off-by: Ashish Kalra ashish.ka...@freescale.com Signed-off-by: Stuart Yoder stuart.yo...@freescale.com Signed-off-by: Dave Liu dave...@freescale.com Signed-off-by: Lan Chunhe-B25806 b25...@freescale.com Signed-off-by: Scott Wood scottw...@freescale.com Signed-off-by: Kim Phillips kim.phill...@freescale.com Signed-off-by: Roy Zang tie-fei.z...@freescale.com Signed-off-by: Timur Tabi ti...@freescale.com Signed-off-by: Andy Fleming aflem...@freescale.com Signed-off-by: York Sun york...@freescale.com Signed-off-by: Kumar Gala ga...@kernel.crashing.org --- MAKEALL |1 + board/freescale/common/Makefile |1 + board/freescale/corenet_ds/Makefile | 55 +++ board/freescale/corenet_ds/config.mk| 30 ++ board/freescale/corenet_ds/corenet_ds.c | 365 + board/freescale/corenet_ds/ddr.c| 176 board/freescale/corenet_ds/law.c| 40 ++ board/freescale/corenet_ds/pci.c| 127 ++ board/freescale/corenet_ds/tlb.c| 104 + boards.cfg |1 + include/configs/P4080DS.h | 36 ++ include/configs/corenet_ds.h| 673 +++ 12 files changed, 1609 insertions(+), 0 deletions(-) create mode 100644 board/freescale/corenet_ds/Makefile create mode 100644 board/freescale/corenet_ds/config.mk create mode 100644 board/freescale/corenet_ds/corenet_ds.c create mode 100644 board/freescale/corenet_ds/ddr.c create mode 100644 board/freescale/corenet_ds/law.c create mode 100644 board/freescale/corenet_ds/pci.c create mode 100644 board/freescale/corenet_ds/tlb.c create mode 100644 include/configs/P4080DS.h create mode 100644 include/configs/corenet_ds.h diff --git a/MAKEALL b/MAKEALL index e495b93..f0da775 100755 --- a/MAKEALL +++ b/MAKEALL @@ -427,6 +427,7 @@ LIST_85xx= \ P2020RDB_NAND \ P2020RDB_SDCARD \ P2020RDB_SPIFLASH \ + P4080DS \ PM854 \ PM856 \ sbc8540 \ diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 2d48d7e..f93045f 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -46,6 +46,7 @@ COBJS-$(CONFIG_MPC8536DS) += ics307_clk.o COBJS-$(CONFIG_MPC8572DS) += ics307_clk.o COBJS-$(CONFIG_P1022DS)+= ics307_clk.o COBJS-$(CONFIG_P2020DS)+= ics307_clk.o +COBJS-$(CONFIG_P4080DS)+= ics307_clk.o SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/freescale/corenet_ds/Makefile b/board/freescale/corenet_ds/Makefile new file mode 100644 index 000..8aa7255 --- /dev/null +++ b/board/freescale/corenet_ds/Makefile @@ -0,0 +1,55 @@ +# +# Copyright 2007-2009 Freescale Semiconductor, Inc. +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).a + +COBJS-y+= $(BOARD).o +COBJS-$(CONFIG_DDR_SPD)+= ddr.o +COBJS-$(CONFIG_PCI)+= pci.o +COBJS-y+= law.o +COBJS-y+= tlb.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB):$(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/freescale/corenet_ds/config.mk b/board/freescale/corenet_ds/config.mk new file mode 100644 index
