Re: [U-Boot] [PATCH 4/4 v2] p1021mds: add QE and UEC support
On Feb 7, 2011, at 3:14 PM, haiying.w...@freescale.com
haiying.w...@freescale.com wrote:
From: Haiying Wang haiying.w...@freescale.com
P1021 has some QE pins which need to be set in pmuxcr register before using QE
functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth
mode.
QE9 and QE12 are set for MII management. QE12 needs to be released after MII
access because QE12 pin is muxed with LBCTL signal.
P1021MDS has to load the microcode from NAND flash, this patchs add support to
load ucode from NAND before initializing qe.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
v2: remove misc_init_r, make changes based on laste commits in u-boot-85xx.git
arch/powerpc/cpu/mpc85xx/speed.c |4 ++
arch/powerpc/include/asm/immap_85xx.h | 13
board/freescale/p1021mds/p1021mds.c | 51 +
drivers/qe/uec.c | 40 +-
include/configs/P1021MDS.h| 44
5 files changed, 151 insertions(+), 1 deletions(-)
Can we split this patch up into the QE parts for P1021 and the board parts for
P1021MDS
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c
b/arch/powerpc/cpu/mpc85xx/speed.c
index f2aa8d0..ae94ee8 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -165,10 +165,14 @@ void get_sys_info (sys_info_t * sysInfo)
#endif
#ifdef CONFIG_QE
+#ifdef CONFIG_P1021
+ sysInfo-freqQE = sysInfo-freqSystemBus;
+#else
qe_ratio = ((gur-porpllsr) MPC85xx_PORPLLSR_QE_RATIO)
MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
sysInfo-freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
#endif
+#endif
#if defined(CONFIG_FSL_LBC)
#if defined(CONFIG_SYS_LBC_LCRR)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 99ecb83..d0fa79b 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1909,6 +1909,19 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR_SD_DATA0x8000
#define MPC85xx_PMUXCR_SDHC_CD0x4000
#define MPC85xx_PMUXCR_SDHC_WP0x2000
+#define MPC85xx_PMUXCR_QE0 0x8000
+#define MPC85xx_PMUXCR_QE1 0x4000
+#define MPC85xx_PMUXCR_QE2 0x2000
+#define MPC85xx_PMUXCR_QE3 0x1000
+#define MPC85xx_PMUXCR_QE4 0x0800
+#define MPC85xx_PMUXCR_QE5 0x0400
+#define MPC85xx_PMUXCR_QE6 0x0200
+#define MPC85xx_PMUXCR_QE7 0x0100
+#define MPC85xx_PMUXCR_QE8 0x0080
+#define MPC85xx_PMUXCR_QE9 0x0040
+#define MPC85xx_PMUXCR_QE100x0020
+#define MPC85xx_PMUXCR_QE110x0010
+#define MPC85xx_PMUXCR_QE120x0008
u32 pmuxcr2;/* Alt. function signal multiplex control 2 */
u8 res6[8];
u32 devdisr;/* Device disable control */
diff --git a/board/freescale/p1021mds/p1021mds.c
b/board/freescale/p1021mds/p1021mds.c
index 2dfcf13..29972f8 100644
--- a/board/freescale/p1021mds/p1021mds.c
+++ b/board/freescale/p1021mds/p1021mds.c
@@ -37,6 +37,45 @@
#include tsec.h
#include netdev.h
+#ifdef CONFIG_QE
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+ /* QE_MUX_MDC */
+ {1, 19, 1, 0, 1}, /* QE_MUX_MDC*/
+ /* QE_MUX_MDIO */
+ {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */
+
+ /* UCC_1_MII */
+ {0, 23, 2, 0, 2}, /* CLK12 */
+ {0, 24, 2, 0, 1}, /* CLK9 */
+ {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */
+ {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */
+ {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */
+ {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
+ {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */
+ {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */
+ {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
+ {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
+ {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B*/
+ {0, 13, 1, 0, 2}, /* ENET1_TX_ER */
+ {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B*/
+ {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B*/
+ {0, 17, 2, 0, 2}, /* ENET1_CRS*/
+ {0, 16, 2, 0, 2}, /* ENET1_COL*/
+
+ /* UCC_5_RMII */
+ {1, 11, 2, 0, 1}, /* CLK13 */
+ {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */
+ {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */
+ {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */
+ {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */
+ {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B*/
+ {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B*/
+ {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B*/
+
+ {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
+};
+#endif
+
int board_early_init_f(void)
{
Re: [U-Boot] [PATCH 4/4 v2] p1021mds: add QE and UEC support
On Tue, 2011-02-08 at 10:52 -0600, Kumar Gala wrote:
+#endif
uec = (uec_private_t *)dev-priv;
if (uec-the_first_run == 0) {
+#ifdef CONFIG_P1021
+ /* reset micrel phy for each UEC */
+ clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 11), BCSR11_ENET_MICRST);
+ udelay(200);
+ setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 11), BCSR11_ENET_MICRST);
+
Hmm, this is board specific, can we not do this in board_*_f or _r?
It did not work to do this in board_*_f/r. The board designer to me to
reset the phy before initializing it for each UEC separately. Here is
the right place to do so.
Haiying
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Re: [U-Boot] [PATCH 4/4 v2] p1021mds: add QE and UEC support
On Tue, 2011-02-08 at 12:09 -0500, Haiying Wang wrote:
On Tue, 2011-02-08 at 10:52 -0600, Kumar Gala wrote:
+#endif
uec = (uec_private_t *)dev-priv;
if (uec-the_first_run == 0) {
+#ifdef CONFIG_P1021
+ /* reset micrel phy for each UEC */
+ clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 11), BCSR11_ENET_MICRST);
+ udelay(200);
+ setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 11), BCSR11_ENET_MICRST);
+
Hmm, this is board specific, can we not do this in board_*_f or _r?
It did not work to do this in board_*_f/r. The board designer to me to
:%s/to me/told me/
reset the phy before initializing it for each UEC separately. Here is
the right place to do so.
Haiying
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Re: [U-Boot] [PATCH 4/4 v2] p1021mds: add QE and UEC support
On Feb 8, 2011, at 11:11 AM, Haiying Wang wrote:
On Tue, 2011-02-08 at 12:09 -0500, Haiying Wang wrote:
On Tue, 2011-02-08 at 10:52 -0600, Kumar Gala wrote:
+#endif
uec = (uec_private_t *)dev-priv;
if (uec-the_first_run == 0) {
+#ifdef CONFIG_P1021
+ /* reset micrel phy for each UEC */
+ clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 11), BCSR11_ENET_MICRST);
+ udelay(200);
+ setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 11), BCSR11_ENET_MICRST);
+
Hmm, this is board specific, can we not do this in board_*_f or _r?
It did not work to do this in board_*_f/r. The board designer to me to
:%s/to me/told me/
reset the phy before initializing it for each UEC separately. Here is
the right place to do so.
Haiying
At a minimum this ifdef should be #ifdef CONFIG_P1021MDS
- k
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[U-Boot] [PATCH 4/4 v2] p1021mds: add QE and UEC support
From: Haiying Wang haiying.w...@freescale.com
P1021 has some QE pins which need to be set in pmuxcr register before using QE
functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth mode.
QE9 and QE12 are set for MII management. QE12 needs to be released after MII
access because QE12 pin is muxed with LBCTL signal.
P1021MDS has to load the microcode from NAND flash, this patchs add support to
load ucode from NAND before initializing qe.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
v2: remove misc_init_r, make changes based on laste commits in u-boot-85xx.git
arch/powerpc/cpu/mpc85xx/speed.c |4 ++
arch/powerpc/include/asm/immap_85xx.h | 13
board/freescale/p1021mds/p1021mds.c | 51 +
drivers/qe/uec.c | 40 +-
include/configs/P1021MDS.h| 44
5 files changed, 151 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index f2aa8d0..ae94ee8 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -165,10 +165,14 @@ void get_sys_info (sys_info_t * sysInfo)
#endif
#ifdef CONFIG_QE
+#ifdef CONFIG_P1021
+ sysInfo-freqQE = sysInfo-freqSystemBus;
+#else
qe_ratio = ((gur-porpllsr) MPC85xx_PORPLLSR_QE_RATIO)
MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
sysInfo-freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
#endif
+#endif
#if defined(CONFIG_FSL_LBC)
#if defined(CONFIG_SYS_LBC_LCRR)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 99ecb83..d0fa79b 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1909,6 +1909,19 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR_SD_DATA 0x8000
#define MPC85xx_PMUXCR_SDHC_CD 0x4000
#define MPC85xx_PMUXCR_SDHC_WP 0x2000
+#define MPC85xx_PMUXCR_QE0 0x8000
+#define MPC85xx_PMUXCR_QE1 0x4000
+#define MPC85xx_PMUXCR_QE2 0x2000
+#define MPC85xx_PMUXCR_QE3 0x1000
+#define MPC85xx_PMUXCR_QE4 0x0800
+#define MPC85xx_PMUXCR_QE5 0x0400
+#define MPC85xx_PMUXCR_QE6 0x0200
+#define MPC85xx_PMUXCR_QE7 0x0100
+#define MPC85xx_PMUXCR_QE8 0x0080
+#define MPC85xx_PMUXCR_QE9 0x0040
+#define MPC85xx_PMUXCR_QE100x0020
+#define MPC85xx_PMUXCR_QE110x0010
+#define MPC85xx_PMUXCR_QE120x0008
u32 pmuxcr2;/* Alt. function signal multiplex control 2 */
u8 res6[8];
u32 devdisr;/* Device disable control */
diff --git a/board/freescale/p1021mds/p1021mds.c
b/board/freescale/p1021mds/p1021mds.c
index 2dfcf13..29972f8 100644
--- a/board/freescale/p1021mds/p1021mds.c
+++ b/board/freescale/p1021mds/p1021mds.c
@@ -37,6 +37,45 @@
#include tsec.h
#include netdev.h
+#ifdef CONFIG_QE
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+ /* QE_MUX_MDC */
+ {1, 19, 1, 0, 1}, /* QE_MUX_MDC*/
+ /* QE_MUX_MDIO */
+ {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */
+
+ /* UCC_1_MII */
+ {0, 23, 2, 0, 2}, /* CLK12 */
+ {0, 24, 2, 0, 1}, /* CLK9 */
+ {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */
+ {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */
+ {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */
+ {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
+ {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */
+ {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */
+ {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
+ {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
+ {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B*/
+ {0, 13, 1, 0, 2}, /* ENET1_TX_ER */
+ {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B*/
+ {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B*/
+ {0, 17, 2, 0, 2}, /* ENET1_CRS*/
+ {0, 16, 2, 0, 2}, /* ENET1_COL*/
+
+ /* UCC_5_RMII */
+ {1, 11, 2, 0, 1}, /* CLK13 */
+ {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */
+ {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */
+ {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */
+ {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */
+ {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B*/
+ {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B*/
+ {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B*/
+
+ {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
+};
+#endif
+
int board_early_init_f(void)
{
@@ -100,6 +139,14 @@ int board_eth_init(bd_t *bis)
tsec_eth_init(bis, tsec_info, num);
+#if defined(CONFIG_UEC_ETH)
+ /* QE0 and QE3 need to be exposed for UCC1 and UCC5 Eth mode */
+
