[U-Boot] [PATCH 4/5] MSM7x27a: USB Gadget support
Signed-off-by: Srikanth Reddy Vintha
---
arch/arm/cpu/armv7/msm7x27a/acpuclock.c|6 +
arch/arm/include/asm/arch-msm7x27a/iomap.h |1 +
arch/arm/include/asm/arch-msm7x27a/irqs.h | 138
include/configs/msm7x27a_surf.h| 13 +--
4 files changed, 151 insertions(+), 7 deletions(-)
create mode 100644 arch/arm/include/asm/arch-msm7x27a/irqs.h
diff --git a/arch/arm/cpu/armv7/msm7x27a/acpuclock.c
b/arch/arm/cpu/armv7/msm7x27a/acpuclock.c
index c144233..7af80ef 100644
--- a/arch/arm/cpu/armv7/msm7x27a/acpuclock.c
+++ b/arch/arm/cpu/armv7/msm7x27a/acpuclock.c
@@ -222,6 +222,12 @@ void acpu_clock_init(void)
udelay(1000);
}
}
+void hsusb_clock_init(void)
+{
+ /* USB local clock control not enabled; use proc comm */
+ usb_clock_init();
+}
+
#ifdef CONFIG_QC_MMC
/* Configure MMC clock */
diff --git a/arch/arm/include/asm/arch-msm7x27a/iomap.h
b/arch/arm/include/asm/arch-msm7x27a/iomap.h
index 4c9d434..bc875ff 100644
--- a/arch/arm/include/asm/arch-msm7x27a/iomap.h
+++ b/arch/arm/include/asm/arch-msm7x27a/iomap.h
@@ -48,6 +48,7 @@
#define MSM_SHARED_BASE 0x0010
+#define MSM_USB_BASE 0xA080
#define MSM_SDC1_BASE 0xA040
#define MSM_SDC3_BASE 0xA060
diff --git a/arch/arm/include/asm/arch-msm7x27a/irqs.h
b/arch/arm/include/asm/arch-msm7x27a/irqs.h
new file mode 100644
index 000..798fd43
--- /dev/null
+++ b/arch/arm/include/asm/arch-msm7x27a/irqs.h
@@ -0,0 +1,138 @@
+/*
+ * Copyright (c) 2008, Google Inc.
+ * All rights reserved.
+ *
+ * (C) Copyright 2012
+ * Larsen & Toubro Infotech Ltd.
+ *
+ * This source code is dual-licensed. You may use it under the terms of the
+ * GNU General Public License version 2, or under the license below.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Google, Inc. nor the names of its contributors
+ * may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _PLATFORM_MSM7K_IRQS_H_
+#define _PLATFORM_MSM7K_IRQS_H_
+
+#define VIC_REG(off) (MSM_VIC_BASE + (off))
+
+#define VIC_INT_SELECT0 VIC_REG(0x) /* 1: FIQ, 0: IRQ */
+#define VIC_INT_SELECT1 VIC_REG(0x0004) /* 1: FIQ, 0: IRQ */
+#define VIC_INT_EN0 VIC_REG(0x0010)
+#define VIC_INT_EN1 VIC_REG(0x0014)
+#define VIC_INT_ENCLEAR0VIC_REG(0x0020)
+#define VIC_INT_ENCLEAR1VIC_REG(0x0024)
+#define VIC_INT_ENSET0VIC_REG(0x0030)
+#define VIC_INT_ENSET1VIC_REG(0x0034)
+#define VIC_INT_TYPE0 VIC_REG(0x0040) /* 1: EDGE, 0: LEVEL */
+#define VIC_INT_TYPE1 VIC_REG(0x0044) /* 1: EDGE, 0: LEVEL */
+#define VIC_INT_POLARITY0 VIC_REG(0x0050) /* 1: NEG, 0: POS */
+#define VIC_INT_POLARITY1 VIC_REG(0x0054) /* 1: NEG, 0: POS */
+#define VIC_NO_PEND_VAL VIC_REG(0x0060)
+#define VIC_INT_MASTERENVIC_REG(0x0064) /* 1: IRQ, 2: FIQ */
+#define VIC_PROTECTIONVIC_REG(0x006C) /* 1: ENABLE */
+#define VIC_CONFIGVIC_REG(0x0068) /* 1: USE ARM1136 VIC */
+#define VIC_IRQ_STATUS0 VIC_REG(0x0080)
+#define VIC_IRQ_STATUS1 VIC_REG(0x0084)
+#define VIC_FIQ_STATUS0 VIC_REG(0x0090)
+#define VIC_FIQ_STATUS1 VIC_REG(0x0094)
+#define VIC_RAW_STATUS0 VIC_REG(0x00A0)
+#define VIC_RAW_STATUS1 VIC_REG(0x00A4)
+#define VIC_INT_CLEAR0VIC_REG(0x00B0)
+#define VIC_INT_CLEAR1VIC_REG(0x00B4)
+#define VIC_SOFTINT0VIC_REG(0x00C0)
+#define VIC_SOFTINT1VIC_REG(0x00C4)
+#define VIC_IRQ_VEC_RDVIC_REG(0x00D0) /* pending int # */
+#define VIC_IRQ_VEC_PEND_RD VIC_REG(0x00D4) /* pending vector addr */
+#define VIC_IRQ_VEC_WR
[U-Boot] [PATCH 4/5] MSM7x27a: USB Gadget support
Signed-off-by: Srikanth Reddy Vintha
---
arch/arm/cpu/armv7/msm7x27a/acpuclock.c|6 +
arch/arm/include/asm/arch-msm7x27a/iomap.h |1 +
arch/arm/include/asm/arch-msm7x27a/irqs.h | 138
include/configs/msm7x27a_surf.h| 13 +--
4 files changed, 151 insertions(+), 7 deletions(-)
create mode 100644 arch/arm/include/asm/arch-msm7x27a/irqs.h
diff --git a/arch/arm/cpu/armv7/msm7x27a/acpuclock.c
b/arch/arm/cpu/armv7/msm7x27a/acpuclock.c
index c144233..7af80ef 100644
--- a/arch/arm/cpu/armv7/msm7x27a/acpuclock.c
+++ b/arch/arm/cpu/armv7/msm7x27a/acpuclock.c
@@ -222,6 +222,12 @@ void acpu_clock_init(void)
udelay(1000);
}
}
+void hsusb_clock_init(void)
+{
+ /* USB local clock control not enabled; use proc comm */
+ usb_clock_init();
+}
+
#ifdef CONFIG_QC_MMC
/* Configure MMC clock */
diff --git a/arch/arm/include/asm/arch-msm7x27a/iomap.h
b/arch/arm/include/asm/arch-msm7x27a/iomap.h
index 4c9d434..bc875ff 100644
--- a/arch/arm/include/asm/arch-msm7x27a/iomap.h
+++ b/arch/arm/include/asm/arch-msm7x27a/iomap.h
@@ -48,6 +48,7 @@
#define MSM_SHARED_BASE 0x0010
+#define MSM_USB_BASE 0xA080
#define MSM_SDC1_BASE 0xA040
#define MSM_SDC3_BASE 0xA060
diff --git a/arch/arm/include/asm/arch-msm7x27a/irqs.h
b/arch/arm/include/asm/arch-msm7x27a/irqs.h
new file mode 100644
index 000..798fd43
--- /dev/null
+++ b/arch/arm/include/asm/arch-msm7x27a/irqs.h
@@ -0,0 +1,138 @@
+/*
+ * Copyright (c) 2008, Google Inc.
+ * All rights reserved.
+ *
+ * (C) Copyright 2012
+ * Larsen & Toubro Infotech Ltd.
+ *
+ * This source code is dual-licensed. You may use it under the terms of the
+ * GNU General Public License version 2, or under the license below.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Google, Inc. nor the names of its contributors
+ * may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _PLATFORM_MSM7K_IRQS_H_
+#define _PLATFORM_MSM7K_IRQS_H_
+
+#define VIC_REG(off) (MSM_VIC_BASE + (off))
+
+#define VIC_INT_SELECT0 VIC_REG(0x) /* 1: FIQ, 0: IRQ */
+#define VIC_INT_SELECT1 VIC_REG(0x0004) /* 1: FIQ, 0: IRQ */
+#define VIC_INT_EN0 VIC_REG(0x0010)
+#define VIC_INT_EN1 VIC_REG(0x0014)
+#define VIC_INT_ENCLEAR0VIC_REG(0x0020)
+#define VIC_INT_ENCLEAR1VIC_REG(0x0024)
+#define VIC_INT_ENSET0VIC_REG(0x0030)
+#define VIC_INT_ENSET1VIC_REG(0x0034)
+#define VIC_INT_TYPE0 VIC_REG(0x0040) /* 1: EDGE, 0: LEVEL */
+#define VIC_INT_TYPE1 VIC_REG(0x0044) /* 1: EDGE, 0: LEVEL */
+#define VIC_INT_POLARITY0 VIC_REG(0x0050) /* 1: NEG, 0: POS */
+#define VIC_INT_POLARITY1 VIC_REG(0x0054) /* 1: NEG, 0: POS */
+#define VIC_NO_PEND_VAL VIC_REG(0x0060)
+#define VIC_INT_MASTERENVIC_REG(0x0064) /* 1: IRQ, 2: FIQ */
+#define VIC_PROTECTIONVIC_REG(0x006C) /* 1: ENABLE */
+#define VIC_CONFIGVIC_REG(0x0068) /* 1: USE ARM1136 VIC */
+#define VIC_IRQ_STATUS0 VIC_REG(0x0080)
+#define VIC_IRQ_STATUS1 VIC_REG(0x0084)
+#define VIC_FIQ_STATUS0 VIC_REG(0x0090)
+#define VIC_FIQ_STATUS1 VIC_REG(0x0094)
+#define VIC_RAW_STATUS0 VIC_REG(0x00A0)
+#define VIC_RAW_STATUS1 VIC_REG(0x00A4)
+#define VIC_INT_CLEAR0VIC_REG(0x00B0)
+#define VIC_INT_CLEAR1VIC_REG(0x00B4)
+#define VIC_SOFTINT0VIC_REG(0x00C0)
+#define VIC_SOFTINT1VIC_REG(0x00C4)
+#define VIC_IRQ_VEC_RDVIC_REG(0x00D0) /* pending int # */
+#define VIC_IRQ_VEC_PEND_RD VIC_REG(0x00D4) /* pending vector addr */
+#define VIC_IRQ_VEC_WR
