mxs_power_clock2pll() does not actually switch the CPU clock to the PLL.
All it does is power-up the PLL and set the CLKCTRL_CLKSEQ_BYPASS_CPU bit
(which was already set by mxs_power_clock2xtal() anyway)
spl_mem_init.c sets up the fractional divisor (which is required to run
the CPU from the PLL) and clears the CLKCTRL_CLKSEQ_BYPASS_CPU bit (which
switches the CPU clock to the PLL)
It makes more sense to power-up the PLL in spl_mem_init.c. While moving
the PLL power-up, we may as well properly configure how the PLL lock is
started and confirmed
Signed-off-by: Graeme Russ gr...@tss-engineering.com
---
arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 31
arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 45 -
2 files changed, 31 insertions(+), 45 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
index a744e5d..af4ed8c 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
@@ -340,10 +340,41 @@ static void mx28_mem_init(void)
}
#endif
+/**
+ * mxs_mem_powerup_pll() - Powerup PLL0
+ *
+ * This function turns on power to PLL0. The CPU clock will be switched to
+ * PLL0 after the fractional divider and SDRAM have been configured.
+ */
+static void mxs_mem_powerup_pll(void)
+{
+ struct mxs_clkctrl_regs *clkctrl_regs =
+ (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+
+ /* Power up PLL0 */
+ debug(SPL: Powering up PLL0\n);
+ setbits_le32(clkctrl_regs-hw_clkctrl_pll0ctrl0,
+CLKCTRL_PLL0CTRL0_POWER);
+
+ /* Toggle FORCE_LOCK to initiate the PLL lock procedure */
+ setbits_le32(clkctrl_regs-hw_clkctrl_pll0ctrl1,
+CLKCTRL_PLL0CTRL1_FORCE_LOCK);
+
+ clrbits_le32(clkctrl_regs-hw_clkctrl_pll0ctrl1,
+CLKCTRL_PLL0CTRL1_FORCE_LOCK);
+
+ /* Wait until the PLL has a stable lock - takes ~50us */
+ while (!(readl(clkctrl_regs-hw_clkctrl_pll0ctrl1)
+CLKCTRL_PLL0CTRL1_LOCK))
+ ;
+}
+
void mxs_mem_init(void)
{
early_delay(11000);
+ mxs_mem_powerup_pll();
+
mxs_mem_init_clock();
mxs_mem_setup_vdda();
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
index e469381..7267fd5 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
@@ -50,39 +50,6 @@ static void mxs_power_clock2xtal(void)
}
/**
- * mxs_power_clock2pll() - Switch CPU core clock source to PLL
- *
- * This function switches the CPU core clock from 24MHz XTAL oscilator
- * to PLL. This can only be called once the PLL has re-locked and once
- * the PLL is stable after reconfiguration.
- */
-static void mxs_power_clock2pll(void)
-{
- struct mxs_clkctrl_regs *clkctrl_regs =
- (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
-
- debug(SPL: Switching CPU core clock source to PLL\n);
-
- /*
-* TODO: Are we really? It looks like we turn on PLL0, but we then
-* set the CLKCTRL_CLKSEQ_BYPASS_CPU bit of the (which was already
-* set by mxs_power_clock2xtal()). Clearing this bit here seems to
-* introduce some instability (causing the CPU core to hang). Maybe
-* we aren't giving PLL0 enough time to stabilise?
-*/
- setbits_le32(clkctrl_regs-hw_clkctrl_pll0ctrl0,
- CLKCTRL_PLL0CTRL0_POWER);
- early_delay(100);
-
- /*
-* TODO: Should the PLL0 FORCE_LOCK bit be set here followed be a
-* wait on the PLL0 LOCK bit?
-*/
- setbits_le32(clkctrl_regs-hw_clkctrl_clkseq,
- CLKCTRL_CLKSEQ_BYPASS_CPU);
-}
-
-/**
* mxs_power_set_auto_restart() - Set the auto-restart bit
*
* This function ungates the RTC block and sets the AUTO_RESTART
@@ -993,12 +960,6 @@ static void mxs_power_configure_power_source(void)
BATTERY_BRWNOUT_BITFIELD_VALUE
POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
mxs_5v_boot();
-
- /*
-* TODO: Do not switch CPU clock to PLL if we are VDD5V is sourced
-* from USB VBUS
-*/
- mxs_power_clock2pll();
#else
if (readl(power_regs-hw_power_sts) POWER_STS_VDD5V_GT_VDDIO) {
batt_ready = mxs_is_batt_ready();
@@ -1021,12 +982,6 @@ static void mxs_power_configure_power_source(void)
mxs_batt_boot();
}
- /*
-* TODO: Do not switch CPU clock to PLL if we are VDD5V is sourced
-* from USB VBUS
-*/
- mxs_power_clock2pll();
-
mxs_init_batt_bo();
#endif
--
1.9.3
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