Control module register addresses are changed from OMAP5
to DRA7XX socs.
So adding the necessary changes for the same.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: R Sricharan r.sricha...@ti.com
---
arch/arm/cpu/armv7/omap5/hw_data.c |5 ++-
arch/arm/cpu/armv7/omap5/prcm-regs.c | 72 ++
arch/arm/include/asm/omap_common.h | 10 +
3 files changed, 85 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c
b/arch/arm/cpu/armv7/omap5/hw_data.c
index 095af01..d42974e 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -550,6 +550,7 @@ void hw_data_init(void)
*prcm = omap5_es1_prcm;
*dplls_data = omap5_dplls_es1;
*omap_vcores = omap5430_volts;
+ *ctrl = omap5_ctrl;
break;
case OMAP5430_ES2_0:
@@ -557,19 +558,19 @@ void hw_data_init(void)
*prcm = omap5_es2_prcm;
*dplls_data = omap5_dplls_es2;
*omap_vcores = omap5430_volts_es2;
+ *ctrl = omap5_ctrl;
break;
case DRA752_ES1_0:
*prcm = dra7xx_prcm;
*dplls_data = dra7xx_dplls;
*omap_vcores = omap5430_volts_es2;
+ *ctrl = dra7xx_ctrl;
break;
default:
printf(\n INVALID OMAP REVISION );
}
-
- *ctrl = omap5_ctrl;
}
void get_ioregs(const struct ctrl_ioregs **regs)
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c
b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index c8f62d1..c2fce11 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -381,6 +381,78 @@ struct omap_sys_ctrl_regs const omap5_ctrl = {
.control_efuse_13 = 0x4AE0CDF8,
};
+struct omap_sys_ctrl_regs const dra7xx_ctrl = {
+ .control_status = 0x4A002134,
+ .control_core_mmr_lock1 = 0x4A002540,
+ .control_core_mmr_lock2 = 0x4A002544,
+ .control_core_mmr_lock3 = 0x4A002548,
+ .control_core_mmr_lock4 = 0x4A00254C,
+ .control_core_mmr_lock5 = 0x4A002550,
+ .control_core_control_io1 = 0x4A002554,
+ .control_core_control_io2 = 0x4A002558,
+ .control_paconf_global = 0x4A002DA0,
+ .control_paconf_mode= 0x4A002DA4,
+ .control_smart1io_padconf_0 = 0x4A002DA8,
+ .control_smart1io_padconf_1 = 0x4A002DAC,
+ .control_smart1io_padconf_2 = 0x4A002DB0,
+ .control_smart2io_padconf_0 = 0x4A002DB4,
+ .control_smart2io_padconf_1 = 0x4A002DB8,
+ .control_smart2io_padconf_2 = 0x4A002DBC,
+ .control_smart3io_padconf_0 = 0x4A002DC0,
+ .control_smart3io_padconf_1 = 0x4A002DC4,
+ .control_pbias = 0x4A002E00,
+ .control_i2c_0 = 0x4A002E04,
+ .control_camera_rx = 0x4A002E08,
+ .control_hdmi_tx_phy= 0x4A002E0C,
+ .control_uniportm = 0x4A002E10,
+ .control_dsiphy = 0x4A002E14,
+ .control_mcbsplp= 0x4A002E18,
+ .control_usb2phycore= 0x4A002E1C,
+ .control_hdmi_1 = 0x4A002E20,
+ .control_hsi= 0x4A002E24,
+ .control_ddr3ch1_0 = 0x4A002E30,
+ .control_ddr3ch2_0 = 0x4A002E34,
+ .control_ddrch1_0 = 0x4A002E38,
+ .control_ddrch1_1 = 0x4A002E3C,
+ .control_ddrch2_0 = 0x4A002E40,
+ .control_ddrch2_1 = 0x4A002E44,
+ .control_lpddr2ch1_0= 0x4A002E48,
+ .control_lpddr2ch1_1= 0x4A002E4C,
+ .control_ddrio_0= 0x4A002E50,
+ .control_ddrio_1= 0x4A002E54,
+ .control_ddrio_2= 0x4A002E58,
+ .control_hyst_1 = 0x4A002E5C,
+ .control_usbb_hsic_control = 0x4A002E60,
+ .control_c2c= 0x4A002E64,
+ .control_core_control_spare_rw = 0x4A002E68,
+ .control_core_control_spare_r = 0x4A002E6C,
+ .control_core_control_spare_r_c0= 0x4A002E70,
+ .control_srcomp_north_side = 0x4A002E74,
+ .control_srcomp_south_side = 0x4A002E78,
+ .control_srcomp_east_side = 0x4A002E7C,
+ .control_srcomp_west_side = 0x4A002E80,
+ .control_srcomp_code_latch = 0x4A002E84,
+ .control_padconf_core_base = 0x4A003400,
+
