Re: [U-Boot] [PATCH 4/7 v3] pci/layerscape: add support for LUT

2016-03-08 Thread Stuart Yoder 


> -Original Message-
> From: york sun
> Sent: Monday, March 07, 2016 4:32 PM
> To: Stuart Yoder ; u-boot@lists.denx.de
> Cc: Prabhakar Kushwaha ; Mingkai Hu 
> ;
> Minghuan Lian ; Yang-Leo Li ;
> marc.zyng...@arm.com
> Subject: Re: [PATCH 4/7 v3] pci/layerscape: add support for LUT
> 
> On 02/26/2016 08:52 AM, Stuart Yoder wrote:
> > From: Stuart Yoder 
> >
> > The per-PCI controller LUT (Look-Up-Table) is a 32-entry table
> > that maps PCI requester IDs (bus/dev/fun) to a stream ID.
> >
> > This patch implements infrastructure to enable LUT initialization:
> >   -define registers offsets
> >   -add an index to 'struct ls_pcie' to track next available slot in LUT
> >   -add function to allocate the next available entry index
> >   -add function to program a LUT entry
> >
> > Signed-off-by: Stuart Yoder 
> > ---
> > -v3
> >-moved LUT #defines to immap_lsch3.h, made index
> > allocator return an int
> >
> >  .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |4 +++
> >  drivers/pci/pcie_layerscape.c  |   29 
> > 
> >  2 files changed, 33 insertions(+)
> >
> > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> > index 91f3ce8..d04e336 100644
> > --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> > +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> > @@ -86,6 +86,10 @@
> >  #define PCIE_LUT_BASE  0x8
> >  #define PCIE_LUT_LCTRL00x7F8
> >  #define PCIE_LUT_DBG   0x7FC
> > +#define PCIE_LUT_UDR(n) (0x800 + (n) * 8)
> > +#define PCIE_LUT_LDR(n) (0x804 + (n) * 8)
> > +#define PCIE_LUT_ENABLE (1 << 31)
> > +#define PCIE_LUT_ENTRY_COUNT32
> >
> >  /* Device Configuration */
> >  #define DCFG_BASE  0x01e0
> > diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
> > index bb29222..8b1e6fb 100644
> > --- a/drivers/pci/pcie_layerscape.c
> > +++ b/drivers/pci/pcie_layerscape.c
> > @@ -93,6 +93,7 @@ struct ls_pcie {
> > void __iomem *dbi;
> > void __iomem *va_cfg0;
> > void __iomem *va_cfg1;
> > +   int next_lut_index;
> > struct pci_controller hose;
> >  };
> >
> > @@ -482,6 +483,33 @@ static void ls_pcie_setup_ep(struct ls_pcie *pcie, 
> > struct
> ls_pcie_info *info)
> > }
> >  }
> >
> > +
> > +/*
> > + * Return next available LUT index.
> > + */
> > +static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
> > +{
> > +   if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
> 
> This causes compiling error on LS1043 targets. LS1043is lsch2 device. Please
> test your patch on all layerscape targets.

Yes, forgot about ls1043...will respin.

Stuart
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Re: [U-Boot] [PATCH 4/7 v3] pci/layerscape: add support for LUT

2016-03-07 Thread york sun 
On 02/26/2016 08:52 AM, Stuart Yoder wrote:
> From: Stuart Yoder 
> 
> The per-PCI controller LUT (Look-Up-Table) is a 32-entry table
> that maps PCI requester IDs (bus/dev/fun) to a stream ID.
> 
> This patch implements infrastructure to enable LUT initialization:
>   -define registers offsets
>   -add an index to 'struct ls_pcie' to track next available slot in LUT
>   -add function to allocate the next available entry index
>   -add function to program a LUT entry
> 
> Signed-off-by: Stuart Yoder 
> ---
> -v3
>-moved LUT #defines to immap_lsch3.h, made index
> allocator return an int
> 
>  .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |4 +++
>  drivers/pci/pcie_layerscape.c  |   29 
> 
>  2 files changed, 33 insertions(+)
> 
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
> b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> index 91f3ce8..d04e336 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> @@ -86,6 +86,10 @@
>  #define PCIE_LUT_BASE0x8
>  #define PCIE_LUT_LCTRL0  0x7F8
>  #define PCIE_LUT_DBG 0x7FC
> +#define PCIE_LUT_UDR(n) (0x800 + (n) * 8)
> +#define PCIE_LUT_LDR(n) (0x804 + (n) * 8)
> +#define PCIE_LUT_ENABLE (1 << 31)
> +#define PCIE_LUT_ENTRY_COUNT32
>  
>  /* Device Configuration */
>  #define DCFG_BASE0x01e0
> diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
> index bb29222..8b1e6fb 100644
> --- a/drivers/pci/pcie_layerscape.c
> +++ b/drivers/pci/pcie_layerscape.c
> @@ -93,6 +93,7 @@ struct ls_pcie {
>   void __iomem *dbi;
>   void __iomem *va_cfg0;
>   void __iomem *va_cfg1;
> + int next_lut_index;
>   struct pci_controller hose;
>  };
>  
> @@ -482,6 +483,33 @@ static void ls_pcie_setup_ep(struct ls_pcie *pcie, 
> struct ls_pcie_info *info)
>   }
>  }
>  
> +
> +/*
> + * Return next available LUT index.
> + */
> +static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
> +{
> + if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)

This causes compiling error on LS1043 targets. LS1043is lsch2 device. Please
test your patch on all layerscape targets.

York
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[U-Boot] [PATCH 4/7 v3] pci/layerscape: add support for LUT

2016-02-26 Thread Stuart Yoder 
From: Stuart Yoder 

The per-PCI controller LUT (Look-Up-Table) is a 32-entry table
that maps PCI requester IDs (bus/dev/fun) to a stream ID.

This patch implements infrastructure to enable LUT initialization:
  -define registers offsets
  -add an index to 'struct ls_pcie' to track next available slot in LUT
  -add function to allocate the next available entry index
  -add function to program a LUT entry

Signed-off-by: Stuart Yoder 
---
-v3
   -moved LUT #defines to immap_lsch3.h, made index
allocator return an int

 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |4 +++
 drivers/pci/pcie_layerscape.c  |   29 
 2 files changed, 33 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 91f3ce8..d04e336 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -86,6 +86,10 @@
 #define PCIE_LUT_BASE  0x8
 #define PCIE_LUT_LCTRL00x7F8
 #define PCIE_LUT_DBG   0x7FC
+#define PCIE_LUT_UDR(n) (0x800 + (n) * 8)
+#define PCIE_LUT_LDR(n) (0x804 + (n) * 8)
+#define PCIE_LUT_ENABLE (1 << 31)
+#define PCIE_LUT_ENTRY_COUNT32
 
 /* Device Configuration */
 #define DCFG_BASE  0x01e0
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index bb29222..8b1e6fb 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -93,6 +93,7 @@ struct ls_pcie {
void __iomem *dbi;
void __iomem *va_cfg0;
void __iomem *va_cfg1;
+   int next_lut_index;
struct pci_controller hose;
 };
 
@@ -482,6 +483,33 @@ static void ls_pcie_setup_ep(struct ls_pcie *pcie, struct 
ls_pcie_info *info)
}
 }
 
+
+/*
+ * Return next available LUT index.
+ */
+static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
+{
+   if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
+   return pcie->next_lut_index++;
+   else
+   return -1;  /* LUT is full */
+}
+
+/*
+ * Program a single LUT entry
+ */
+static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid,
+u32 streamid)
+{
+   void __iomem *lut;
+
+   lut = pcie->dbi + PCIE_LUT_BASE;
+
+   /* leave mask as all zeroes, want to match all bits */
+   writel((devid << 16), lut + PCIE_LUT_UDR(index));
+   writel(streamid | PCIE_LUT_ENABLE, lut + PCIE_LUT_LDR(index));
+}
+
 int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info 
*info)
 {
struct ls_pcie *pcie;
@@ -513,6 +541,7 @@ int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, 
struct ls_pcie_info *info)
pcie->va_cfg1 = map_physmem(info->cfg1_phys,
info->cfg1_size,
MAP_NOCACHE);
+   pcie->next_lut_index = 0;
 
/* outbound memory */
pci_set_region(&hose->regions[0],
-- 
1.7.9.5

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