Re: [U-Boot] [PATCH 6/6] p1021mds: add QE and UEC support
On Mon, 31 Jan 2011 22:14:45 -0500 Haiying Wang haiying.w...@freescale.com wrote: On Mon, 2011-01-31 at 15:28 -0600, Kumar Gala wrote: On Jan 31, 2011, at 2:50 PM, Haiying Wang wrote: On Mon, 2011-01-31 at 21:11 +0100, Wolfgang Denk wrote: +#ifdef CONFIG_P1021 + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + /* QE9 and QE12 need to be set for enabling QE MII managment signals */ + setbits_be32(gur-pmuxcr, MPC85xx_PMUXCR_QE9); + setbits_be32(gur-pmuxcr, MPC85xx_PMUXCR_QE12); +#endif ... Can we please avoid having board specific code in common files? I wish I could, but only P1021 has such pin mux problems. If this is really necessary, it shoud be a feature-specific #define, not a board specific one. I don't know whether this *feature* will show up on other SoC. But if you insist, I can use CONFIG_QE_PIN_MUX. Thanks. Haiying I think pin muxing is a board level decision so it seems like board code is the right place for it. If it is a one time setting, there should be no problem to put it into board code. But these pin settings need to be done before any usage of phy read/write (accessing MDIO/MDC), and need to be released after the usage of phy, thus the devices connected to eLBC like NAND flash/BCSR can be accessed. If we use board code to set/release the pin, we don't know when the phy access and nand flash access will happen. Is this actually a board issue or an SoC issue? -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 6/6] p1021mds: add QE and UEC support
On Tue, 2011-02-01 at 10:50 -0600, Scott Wood wrote: If it is a one time setting, there should be no problem to put it into board code. But these pin settings need to be done before any usage of phy read/write (accessing MDIO/MDC), and need to be released after the usage of phy, thus the devices connected to eLBC like NAND flash/BCSR can be accessed. If we use board code to set/release the pin, we don't know when the phy access and nand flash access will happen. Is this actually a board issue or an SoC issue? It is not a board issue. It is a SoC *feature*. Too many pins are muxed on P1021. For this case, LBCTL of eLBC is muxed with QE's CE_PB[20] which is used for MDIO signal. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 6/6] p1021mds: add QE and UEC support
On Feb 1, 2011, at 11:01 AM, Haiying Wang wrote: On Tue, 2011-02-01 at 10:50 -0600, Scott Wood wrote: If it is a one time setting, there should be no problem to put it into board code. But these pin settings need to be done before any usage of phy read/write (accessing MDIO/MDC), and need to be released after the usage of phy, thus the devices connected to eLBC like NAND flash/BCSR can be accessed. If we use board code to set/release the pin, we don't know when the phy access and nand flash access will happen. Is this actually a board issue or an SoC issue? It is not a board issue. It is a SoC *feature*. Too many pins are muxed on P1021. For this case, LBCTL of eLBC is muxed with QE's CE_PB[20] which is used for MDIO signal. Haiying But its a board decision on how they want to utilize those pins and for what feature. - k ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 6/6] p1021mds: add QE and UEC support
On Tue, 2011-02-01 at 13:15 -0600, Kumar Gala wrote: On Feb 1, 2011, at 11:01 AM, Haiying Wang wrote: On Tue, 2011-02-01 at 10:50 -0600, Scott Wood wrote: If it is a one time setting, there should be no problem to put it into board code. But these pin settings need to be done before any usage of phy read/write (accessing MDIO/MDC), and need to be released after the usage of phy, thus the devices connected to eLBC like NAND flash/BCSR can be accessed. If we use board code to set/release the pin, we don't know when the phy access and nand flash access will happen. Is this actually a board issue or an SoC issue? It is not a board issue. It is a SoC *feature*. Too many pins are muxed on P1021. For this case, LBCTL of eLBC is muxed with QE's CE_PB[20] which is used for MDIO signal. Haiying But its a board decision on how they want to utilize those pins and for what feature. Yes, you can say that. If the board doesn't have QE UCC ETH support at all, we won't have to add such code in QE driver. But if there is QE UCC ETH on board, we have no choice to decide which pins to use. We definitely need to use CE_PB[20] for MDIO signal, there is no other GPIO pins to use for QE's MDIO. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 6/6] p1021mds: add QE and UEC support
On Feb 1, 2011, at 1:46 PM, Haiying Wang wrote: On Tue, 2011-02-01 at 13:15 -0600, Kumar Gala wrote: On Feb 1, 2011, at 11:01 AM, Haiying Wang wrote: On Tue, 2011-02-01 at 10:50 -0600, Scott Wood wrote: If it is a one time setting, there should be no problem to put it into board code. But these pin settings need to be done before any usage of phy read/write (accessing MDIO/MDC), and need to be released after the usage of phy, thus the devices connected to eLBC like NAND flash/BCSR can be accessed. If we use board code to set/release the pin, we don't know when the phy access and nand flash access will happen. Is this actually a board issue or an SoC issue? It is not a board issue. It is a SoC *feature*. Too many pins are muxed on P1021. For this case, LBCTL of eLBC is muxed with QE's CE_PB[20] which is used for MDIO signal. Haiying But its a board decision on how they want to utilize those pins and for what feature. Yes, you can say that. If the board doesn't have QE UCC ETH support at all, we won't have to add such code in QE driver. But if there is QE UCC ETH on board, we have no choice to decide which pins to use. We definitely need to use CE_PB[20] for MDIO signal, there is no other GPIO pins to use for QE's MDIO. Haiying If that case and controlled by some CONFIG_QE_* define than we clearly can make the choice in non-board specific code. - k ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 6/6] p1021mds: add QE and UEC support
From: Haiying Wang haiying.w...@freescale.com
P1021 has some QE pins which need to be set in pmuxcr register before using QE
functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth mode.
QE9 and QE12 are set for MII management. QE12 needs to be released after MII
access because QE12 pin is muxed with LBCTL signal.
P1021MDS has to load the microcode from NAND flash, this patch defines
misc_init_r() for loading ucode and initializing qe.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
arch/powerpc/cpu/mpc85xx/speed.c |4 ++
arch/powerpc/include/asm/immap_85xx.h | 13 +
board/freescale/p1021mds/p1021mds.c | 83 +
drivers/qe/uec.c | 40 +++-
include/configs/P1021MDS.h| 47 ++
5 files changed, 186 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index f2aa8d0..ae94ee8 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -165,10 +165,14 @@ void get_sys_info (sys_info_t * sysInfo)
#endif
#ifdef CONFIG_QE
+#ifdef CONFIG_P1021
+ sysInfo-freqQE = sysInfo-freqSystemBus;
+#else
qe_ratio = ((gur-porpllsr) MPC85xx_PORPLLSR_QE_RATIO)
MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
sysInfo-freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
#endif
+#endif
#if defined(CONFIG_FSL_LBC)
#if defined(CONFIG_SYS_LBC_LCRR)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 77e3629..9b7de6b 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1909,6 +1909,19 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR_SD_DATA 0x8000
#define MPC85xx_PMUXCR_SDHC_CD 0x4000
#define MPC85xx_PMUXCR_SDHC_WP 0x2000
+#define MPC85xx_PMUXCR_QE0 0x8000
+#define MPC85xx_PMUXCR_QE1 0x4000
+#define MPC85xx_PMUXCR_QE2 0x2000
+#define MPC85xx_PMUXCR_QE3 0x1000
+#define MPC85xx_PMUXCR_QE4 0x0800
+#define MPC85xx_PMUXCR_QE5 0x0400
+#define MPC85xx_PMUXCR_QE6 0x0200
+#define MPC85xx_PMUXCR_QE7 0x0100
+#define MPC85xx_PMUXCR_QE8 0x0080
+#define MPC85xx_PMUXCR_QE9 0x0040
+#define MPC85xx_PMUXCR_QE100x0020
+#define MPC85xx_PMUXCR_QE110x0010
+#define MPC85xx_PMUXCR_QE120x0008
u32 pmuxcr2;/* Alt. function signal multiplex control 2 */
u8 res6[8];
u32 devdisr;/* Device disable control */
diff --git a/board/freescale/p1021mds/p1021mds.c
b/board/freescale/p1021mds/p1021mds.c
index c7a7e57..e1ee1cf 100644
--- a/board/freescale/p1021mds/p1021mds.c
+++ b/board/freescale/p1021mds/p1021mds.c
@@ -37,6 +37,54 @@
#include tsec.h
#include netdev.h
+#ifdef CONFIG_QE
+#ifdef CONFIG_SYS_QE_FW_IN_NAND
+#include nand.h
+#include asm/errno.h
+#endif
+extern void qe_init(uint qe_base);
+extern void qe_reset(void);
+#endif
+
+#ifdef CONFIG_QE
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+ /* QE_MUX_MDC */
+ {1, 19, 1, 0, 1}, /* QE_MUX_MDC*/
+ /* QE_MUX_MDIO */
+ {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */
+
+ /* UCC_1_MII */
+ {0, 23, 2, 0, 2}, /* CLK12 */
+ {0, 24, 2, 0, 1}, /* CLK9 */
+ {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */
+ {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */
+ {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */
+ {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
+ {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */
+ {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */
+ {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
+ {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
+ {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B*/
+ {0, 13, 1, 0, 2}, /* ENET1_TX_ER */
+ {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B*/
+ {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B*/
+ {0, 17, 2, 0, 2}, /* ENET1_CRS*/
+ {0, 16, 2, 0, 2}, /* ENET1_COL*/
+
+ /* UCC_5_RMII */
+ {1, 11, 2, 0, 1}, /* CLK13 */
+ {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */
+ {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */
+ {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */
+ {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */
+ {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B*/
+ {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B*/
+ {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B*/
+
+ {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
+};
+#endif
+
int board_early_init_f(void)
{
@@ -100,6 +148,14 @@ int board_eth_init(bd_t *bis)
tsec_eth_init(bis, tsec_info, num);
+#if defined(CONFIG_UEC_ETH)
+ /* QE0 and QE3
Re: [U-Boot] [PATCH 6/6] p1021mds: add QE and UEC support
Dear haiying.w...@freescale.com,
In message 1296499317-26616-7-git-send-email-haiying.w...@freescale.com you
wrote:
From: Haiying Wang haiying.w...@freescale.com
P1021 has some QE pins which need to be set in pmuxcr register before using QE
functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth
mode.
QE9 and QE12 are set for MII management. QE12 needs to be released after MII
access because QE12 pin is muxed with LBCTL signal.
P1021MDS has to load the microcode from NAND flash, this patch defines
misc_init_r() for loading ucode and initializing qe.
...
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index 282ab23..04d7987 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
...
+#ifdef CONFIG_P1021
+#define BCSR11_ENET_MICRST 0x20
+#endif
/* Default UTBIPAR SMI address */
#ifndef CONFIG_UTBIPAR_INIT_TBIPA
@@ -588,9 +591,25 @@ static void phy_change(struct eth_device *dev)
{
uec_private_t *uec = (uec_private_t *)dev-priv;
+#ifdef CONFIG_P1021
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+ /* QE9 and QE12 need to be set for enabling QE MII managment signals */
+ setbits_be32(gur-pmuxcr, MPC85xx_PMUXCR_QE9);
+ setbits_be32(gur-pmuxcr, MPC85xx_PMUXCR_QE12);
+#endif
...
Can we please avoid having board specific code in common files?
If this is really necessary, it shoud be a feature-specific #define,
not a board specific one.
@@ -425,6 +469,8 @@
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#endif
+#define CONFIG_E1000
In which way is this change related to this commit?
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
It is better to marry than to burn.
- Bible ``I Corinthians'' ch. 7, v. 9
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Re: [U-Boot] [PATCH 6/6] p1021mds: add QE and UEC support
On Mon, 2011-01-31 at 21:11 +0100, Wolfgang Denk wrote: +#ifdef CONFIG_P1021 + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + /* QE9 and QE12 need to be set for enabling QE MII managment signals */ + setbits_be32(gur-pmuxcr, MPC85xx_PMUXCR_QE9); + setbits_be32(gur-pmuxcr, MPC85xx_PMUXCR_QE12); +#endif ... Can we please avoid having board specific code in common files? I wish I could, but only P1021 has such pin mux problems. If this is really necessary, it shoud be a feature-specific #define, not a board specific one. I don't know whether this *feature* will show up on other SoC. But if you insist, I can use CONFIG_QE_PIN_MUX. Thanks. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 6/6] p1021mds: add QE and UEC support
On Jan 31, 2011, at 2:50 PM, Haiying Wang wrote: On Mon, 2011-01-31 at 21:11 +0100, Wolfgang Denk wrote: +#ifdef CONFIG_P1021 + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + /* QE9 and QE12 need to be set for enabling QE MII managment signals */ + setbits_be32(gur-pmuxcr, MPC85xx_PMUXCR_QE9); + setbits_be32(gur-pmuxcr, MPC85xx_PMUXCR_QE12); +#endif ... Can we please avoid having board specific code in common files? I wish I could, but only P1021 has such pin mux problems. If this is really necessary, it shoud be a feature-specific #define, not a board specific one. I don't know whether this *feature* will show up on other SoC. But if you insist, I can use CONFIG_QE_PIN_MUX. Thanks. Haiying I think pin muxing is a board level decision so it seems like board code is the right place for it. - k ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 6/6] p1021mds: add QE and UEC support
On Mon, 2011-01-31 at 15:28 -0600, Kumar Gala wrote: On Jan 31, 2011, at 2:50 PM, Haiying Wang wrote: On Mon, 2011-01-31 at 21:11 +0100, Wolfgang Denk wrote: +#ifdef CONFIG_P1021 + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + /* QE9 and QE12 need to be set for enabling QE MII managment signals */ + setbits_be32(gur-pmuxcr, MPC85xx_PMUXCR_QE9); + setbits_be32(gur-pmuxcr, MPC85xx_PMUXCR_QE12); +#endif ... Can we please avoid having board specific code in common files? I wish I could, but only P1021 has such pin mux problems. If this is really necessary, it shoud be a feature-specific #define, not a board specific one. I don't know whether this *feature* will show up on other SoC. But if you insist, I can use CONFIG_QE_PIN_MUX. Thanks. Haiying I think pin muxing is a board level decision so it seems like board code is the right place for it. If it is a one time setting, there should be no problem to put it into board code. But these pin settings need to be done before any usage of phy read/write (accessing MDIO/MDC), and need to be released after the usage of phy, thus the devices connected to eLBC like NAND flash/BCSR can be accessed. If we use board code to set/release the pin, we don't know when the phy access and nand flash access will happen. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
