PSCI doesn't need any pen-related code, as it interacts directly
with the power controller.
Make these sections depend on CONFIG_ARMV7_PSCI not being set.
Signed-off-by: Marc Zyngier <marc.zyng...@arm.com>
---
arch/arm/cpu/armv7/nonsec_virt.S | 2 ++
arch/arm/cpu/armv7/virt-v7.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
index bbacbce..c5a8347 100644
--- a/arch/arm/cpu/armv7/nonsec_virt.S
+++ b/arch/arm/cpu/armv7/nonsec_virt.S
@@ -68,6 +68,7 @@ _hyp_trap:
mov pc, lr @ do no switch modes, but
@ return to caller
+#ifndef CONFIG_ARMV7_PSCI
/*
* Secondary CPUs start here and call the code for the core specific parts
* of the non-secure and HYP mode transition. The GIC distributor specific
@@ -93,6 +94,7 @@ ENTRY(_smp_pen)
adr r0, _smp_pen @ do not use this address again
b smp_waitloop @ wait for IPIs, board specific
ENDPROC(_smp_pen)
+#endif
/*
* Switch a core to non-secure state.
diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c
index 2cd604f..55f0bbf 100644
--- a/arch/arm/cpu/armv7/virt-v7.c
+++ b/arch/arm/cpu/armv7/virt-v7.c
@@ -147,8 +147,10 @@ int armv7_switch_nonsec(void)
for (i = 1; i <= itlinesnr; i++)
writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i);
+#ifndef CONFIG_ARMV7_PSCI
smp_set_core_boot_addr((unsigned long)_smp_pen, -1);
smp_kick_all_cpus();
+#endif
/* call the non-sec switching code on this CPU also */
_nonsec_init();
--
1.8.2.3
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