Re: [U-Boot] [PATCH 6/9] x86: ivybridge: Use CONFIG_ENABLE_MRC_CACHE option
On 18 October 2015 at 20:23, Bin Meng wrote: > Hi Simon, > > On Mon, Oct 19, 2015 at 5:55 AM, Simon Glass wrote: >> Use this option instead of a private CONFIG_CACHE_MRC_BIN option. >> > > The CONFIG_CACHE_MRC_BIN option seems to be used to program the MTRR > for the mrc.bin text range to make it run faster. It is nothing > related to the MRC cache data that the CONFIG_ENABLE_MRC_CACHE option > is about. OK, I'll just drop this patch. > >> Signed-off-by: Simon Glass >> --- >> >> arch/x86/cpu/ivybridge/Kconfig | 6 -- >> arch/x86/cpu/ivybridge/car.S | 4 ++-- >> 2 files changed, 2 insertions(+), 8 deletions(-) >> [snip] ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 6/9] x86: ivybridge: Use CONFIG_ENABLE_MRC_CACHE option
Hi Simon, On Mon, Oct 19, 2015 at 5:55 AM, Simon Glass wrote: > Use this option instead of a private CONFIG_CACHE_MRC_BIN option. > The CONFIG_CACHE_MRC_BIN option seems to be used to program the MTRR for the mrc.bin text range to make it run faster. It is nothing related to the MRC cache data that the CONFIG_ENABLE_MRC_CACHE option is about. > Signed-off-by: Simon Glass > --- > > arch/x86/cpu/ivybridge/Kconfig | 6 -- > arch/x86/cpu/ivybridge/car.S | 4 ++-- > 2 files changed, 2 insertions(+), 8 deletions(-) > > diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig > index 0e249a4..c3f324e 100644 > --- a/arch/x86/cpu/ivybridge/Kconfig > +++ b/arch/x86/cpu/ivybridge/Kconfig > @@ -8,12 +8,10 @@ > > config NORTHBRIDGE_INTEL_SANDYBRIDGE > bool > - select CACHE_MRC_BIN > select CPU_INTEL_MODEL_206AX > > config NORTHBRIDGE_INTEL_IVYBRIDGE > bool > - select CACHE_MRC_BIN > select CPU_INTEL_MODEL_306AX > > if NORTHBRIDGE_INTEL_SANDYBRIDGE > @@ -136,8 +134,4 @@ config SOCKET_SPECIFIC_OPTIONS # dummy > select SSE > select CACHE_AS_RAM > > -config CACHE_MRC_BIN > - bool > - default n > - > endif > diff --git a/arch/x86/cpu/ivybridge/car.S b/arch/x86/cpu/ivybridge/car.S > index 407e451..770ef17 100644 > --- a/arch/x86/cpu/ivybridge/car.S > +++ b/arch/x86/cpu/ivybridge/car.S > @@ -145,7 +145,7 @@ clear_mtrrs: > wrmsr > > post_code(POST_CAR_ROM_CACHE) > -#ifdef CONFIG_CACHE_MRC_BIN > +#ifdef CONFIG_ENABLE_MRC_CACHE > /* Enable caching for ram init code to run faster */ > movl$MTRR_PHYS_BASE_MSR(2), %ecx > movl$(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax > @@ -200,7 +200,7 @@ car_uninit: > andl$~1, %eax > wrmsr > > -#ifdef CONFIG_CACHE_MRC_BIN > +#ifdef CONFIG_ENABLE_MRC_CACHE > /* Clear the MTRR that was used to cache MRC */ > xorl%eax, %eax > xorl%edx, %edx > -- Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 6/9] x86: ivybridge: Use CONFIG_ENABLE_MRC_CACHE option
Use this option instead of a private CONFIG_CACHE_MRC_BIN option. Signed-off-by: Simon Glass --- arch/x86/cpu/ivybridge/Kconfig | 6 -- arch/x86/cpu/ivybridge/car.S | 4 ++-- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig index 0e249a4..c3f324e 100644 --- a/arch/x86/cpu/ivybridge/Kconfig +++ b/arch/x86/cpu/ivybridge/Kconfig @@ -8,12 +8,10 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE bool - select CACHE_MRC_BIN select CPU_INTEL_MODEL_206AX config NORTHBRIDGE_INTEL_IVYBRIDGE bool - select CACHE_MRC_BIN select CPU_INTEL_MODEL_306AX if NORTHBRIDGE_INTEL_SANDYBRIDGE @@ -136,8 +134,4 @@ config SOCKET_SPECIFIC_OPTIONS # dummy select SSE select CACHE_AS_RAM -config CACHE_MRC_BIN - bool - default n - endif diff --git a/arch/x86/cpu/ivybridge/car.S b/arch/x86/cpu/ivybridge/car.S index 407e451..770ef17 100644 --- a/arch/x86/cpu/ivybridge/car.S +++ b/arch/x86/cpu/ivybridge/car.S @@ -145,7 +145,7 @@ clear_mtrrs: wrmsr post_code(POST_CAR_ROM_CACHE) -#ifdef CONFIG_CACHE_MRC_BIN +#ifdef CONFIG_ENABLE_MRC_CACHE /* Enable caching for ram init code to run faster */ movl$MTRR_PHYS_BASE_MSR(2), %ecx movl$(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax @@ -200,7 +200,7 @@ car_uninit: andl$~1, %eax wrmsr -#ifdef CONFIG_CACHE_MRC_BIN +#ifdef CONFIG_ENABLE_MRC_CACHE /* Clear the MTRR that was used to cache MRC */ xorl%eax, %eax xorl%edx, %edx -- 2.6.0.rc2.230.g3dd15c0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
