Re: [U-Boot] [PATCH V2] mx28: fix SPL code to make USB booting work
On 06.02.2012 16:29, Marek Vasut wrote:
This patch fixes booting i.MX28 CPUs via USB download.
In this mode the CPU's bootrom implements a USB HID device that
accepts a bootstream.
When downloading the bootstream via USB, first the SPL code is
received and executed. Then the u-boot image is received and
called.
The USB bootmode is interrupt driven.
This patch fixes two things:
1) The ARM's fast interrupt mode is disabled when the SPL code
has been run. So save and restore the CPSR register.
2) The exception vector location is set back to bootrom space to
make the USB interrupts work again. The SPL code needs to change this
option for the ram size probing.
Signed-off-by: Matthias Fuchs matthias.fu...@esd.eu
---
changes in v2:
- store old SPSR on stack instead of jiggling around with some bits
- remove #ifndef CONFIG_SKIP_LOWLEVEL_INIT
arch/arm/cpu/arm926ejs/mx28/start.S | 15 +++
1 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/mx28/start.S
b/arch/arm/cpu/arm926ejs/mx28/start.S index 2cd4d73..69d911b 100644
--- a/arch/arm/cpu/arm926ejs/mx28/start.S
+++ b/arch/arm/cpu/arm926ejs/mx28/start.S
@@ -171,6 +171,7 @@ _reset:
* set the cpu to SVC32 mode
*/
mrs r0,cpsr
+push{r0}
bic r0,r0,#0x1f
orr r0,r0,#0xd3
msr cpsr,r0
@@ -185,6 +186,20 @@ _reset:
bl board_init_ll
+/*
+ * restore bootrom's cpu mode (especially FIQ)
+ */
+pop {r0}
+msr cpsr,r0
+
+/*
+ * set exception vector location back to bootrom space.
+ * (required by bootrom for USB boot)
+ */
+mrc p15, 0, r0, c1, c0, 0
+orr r0, r0, #0x2000 /* set bit 13 'V' */
+mcr p15, 0, r0, c1, c0, 0
Maybe you can save this register too, like you did with CPSR?
Can do.
Done. Works. Patch V3 follows.
Otherwise, it looks good.
btw plain push r0 doesn't work?
No.
Matthias
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[U-Boot] [PATCH V2] mx28: fix SPL code to make USB booting work
This patch fixes booting i.MX28 CPUs via USB download.
In this mode the CPU's bootrom implements a USB HID device that
accepts a bootstream.
When downloading the bootstream via USB, first the SPL code is
received and executed. Then the u-boot image is received and
called.
The USB bootmode is interrupt driven.
This patch fixes two things:
1) The ARM's fast interrupt mode is disabled when the SPL code
has been run. So save and restore the CPSR register.
2) The exception vector location is set back to bootrom space to
make the USB interrupts work again. The SPL code needs to change this
option for the ram size probing.
Signed-off-by: Matthias Fuchs matthias.fu...@esd.eu
---
changes in v2:
- store old SPSR on stack instead of jiggling around with some bits
- remove #ifndef CONFIG_SKIP_LOWLEVEL_INIT
arch/arm/cpu/arm926ejs/mx28/start.S | 15 +++
1 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/mx28/start.S
b/arch/arm/cpu/arm926ejs/mx28/start.S
index 2cd4d73..69d911b 100644
--- a/arch/arm/cpu/arm926ejs/mx28/start.S
+++ b/arch/arm/cpu/arm926ejs/mx28/start.S
@@ -171,6 +171,7 @@ _reset:
* set the cpu to SVC32 mode
*/
mrs r0,cpsr
+ push{r0}
bic r0,r0,#0x1f
orr r0,r0,#0xd3
msr cpsr,r0
@@ -185,6 +186,20 @@ _reset:
bl board_init_ll
+ /*
+* restore bootrom's cpu mode (especially FIQ)
+*/
+ pop {r0}
+ msr cpsr,r0
+
+ /*
+* set exception vector location back to bootrom space.
+* (required by bootrom for USB boot)
+*/
+ mrc p15, 0, r0, c1, c0, 0
+ orr r0, r0, #0x2000 /* set bit 13 'V' */
+ mcr p15, 0, r0, c1, c0, 0
+
pop {r0-r12,r14}
bx lr
--
1.6.1
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Re: [U-Boot] [PATCH V2] mx28: fix SPL code to make USB booting work
This patch fixes booting i.MX28 CPUs via USB download.
In this mode the CPU's bootrom implements a USB HID device that
accepts a bootstream.
When downloading the bootstream via USB, first the SPL code is
received and executed. Then the u-boot image is received and
called.
The USB bootmode is interrupt driven.
This patch fixes two things:
1) The ARM's fast interrupt mode is disabled when the SPL code
has been run. So save and restore the CPSR register.
2) The exception vector location is set back to bootrom space to
make the USB interrupts work again. The SPL code needs to change this
option for the ram size probing.
Signed-off-by: Matthias Fuchs matthias.fu...@esd.eu
---
changes in v2:
- store old SPSR on stack instead of jiggling around with some bits
- remove #ifndef CONFIG_SKIP_LOWLEVEL_INIT
arch/arm/cpu/arm926ejs/mx28/start.S | 15 +++
1 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/mx28/start.S
b/arch/arm/cpu/arm926ejs/mx28/start.S index 2cd4d73..69d911b 100644
--- a/arch/arm/cpu/arm926ejs/mx28/start.S
+++ b/arch/arm/cpu/arm926ejs/mx28/start.S
@@ -171,6 +171,7 @@ _reset:
* set the cpu to SVC32 mode
*/
mrs r0,cpsr
+ push{r0}
bic r0,r0,#0x1f
orr r0,r0,#0xd3
msr cpsr,r0
@@ -185,6 +186,20 @@ _reset:
bl board_init_ll
+ /*
+ * restore bootrom's cpu mode (especially FIQ)
+ */
+ pop {r0}
+ msr cpsr,r0
+
+ /*
+ * set exception vector location back to bootrom space.
+ * (required by bootrom for USB boot)
+ */
+ mrc p15, 0, r0, c1, c0, 0
+ orr r0, r0, #0x2000 /* set bit 13 'V' */
+ mcr p15, 0, r0, c1, c0, 0
Maybe you can save this register too, like you did with CPSR?
Otherwise, it looks good.
btw plain push r0 doesn't work?
M
+
pop {r0-r12,r14}
bx lr
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