Re: [U-Boot] [PATCH V2 2/2] net: add driver for Synopsys Ethernet QoS device
On 10/11/2016 05:41 PM, Joe Hershberger wrote: On Tue, Oct 4, 2016 at 12:45 AM, Stephen Warren wrote: From: Stephen Warren This driver supports the Synopsys Designware Ethernet QoS (Quality of Service) a/k/a eqos IP block, which is a different design than the HW supported by the existing designware.c driver. The IP supports many options for bus type, clocking/reset structure, and feature list. This driver currently supports the specific configuration used in NVIDIA's Tegra186 chip, but should be extensible to other combinations quite easily, as explained in the source. diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c +/* + * This represents the "Transmit Normal Descriptor (Read Format). The format It looks like I missed a trailing " over here --> ^ + * written by HW is different, except for the OWN bit in the flags field. Field "The format written by HW is different, except for the OWN bit in the flags field." This sentence is confusing. Different how? If it's written by HW, isn't it read by driver? Hence it's this format? What is this "Read Format" naming convention? There's a descriptor in memory. SW writes data to it in one format (the "write format") and HW consumes that. Once HW has completed the work associated with the descriptor, if re-writes the entire contents in a completely different format (the "read format"). The only commonality between the two formats is the location of the OWN bit which indicates whether SW has written the data and HW now owns the descriptor, or whether HW has written the data and SW owns the descriptor. The current driver doesn't interpret any of the bits that HW writes except for the OWN bit, which tells SW that HW has finished processing the packet associated with the descriptor. Other fields (e.g. timestamps IIRC) are ignored. "read format" and "write format" are terms from the Synopsis documentation. + * naming assumes SW places uses single buffer per descriptor, rather than There's "a" missing --> ^ + * separate header/payload buffers, such that a single 64-bit pointer is used. This sentence is also odd. Is this copied from a data sheet that was processed through Google translate? There are multiple possible formats for the descriptor SW writes. One allows two 32-bit buffer pointers (e.g. packet header and body) too be included in the descriptor and the other allows a single 64-bit buffer to be included in the descriptor. The descriptions do perhaps rely on terminology from the Synopsis documentation, but without that reliance, the comment would need to duplicate rather a lot of the Synopsis documentation, which would be problematic. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 2/2] net: add driver for Synopsys Ethernet QoS device
On Tue, Oct 4, 2016 at 12:45 AM, Stephen Warren wrote:
> From: Stephen Warren
>
> This driver supports the Synopsys Designware Ethernet QoS (Quality of
> Service) a/k/a eqos IP block, which is a different design than the HW
> supported by the existing designware.c driver. The IP supports many
> options for bus type, clocking/reset structure, and feature list. This
> driver currently supports the specific configuration used in NVIDIA's
> Tegra186 chip, but should be extensible to other combinations quite
> easily, as explained in the source.
>
> Signed-off-by: Stephen Warren
> Reviewed-by: Simon Glass # V1
> ---
> v2:
> * Add note about x86 IO coherency.
> * Use wait_bit() where possible.
> * Use a struct definition of the RX and TX descriptors.
> ---
> drivers/net/Kconfig | 11 +
> drivers/net/Makefile |1 +
> drivers/net/dwc_eth_qos.c | 1497
> +
> 3 files changed, 1509 insertions(+)
> create mode 100644 drivers/net/dwc_eth_qos.c
>
snip...
> diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
> new file mode 100644
> index ..f41aba97a494
> --- /dev/null
> +++ b/drivers/net/dwc_eth_qos.c
snip...
> +/*
> + * Warn if the cache-line size is larger than the descriptor size. In such
> + * cases the driver will likely fail because the CPU needs to flush the cache
> + * when requeuing RX buffers, therefore descriptors written by the hardware
> + * may be discarded. Architectures with full IO coherence, such as x86, do
> not
> + * experience this issue, and hence are excluded from this condition.
Great, thanks.
> + *
> + * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause
> + * the driver to allocate descriptors from a pool of non-cached memory.
> + */
> +#if EQOS_DESCRIPTOR_SIZE < ARCH_DMA_MINALIGN
> +#if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
> + !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_X86)
> +#warning Cache line size is larger than descriptor size
> +#endif
> +#endif
> +
> +/*
> + * This represents the "Transmit Normal Descriptor (Read Format). The format
> + * written by HW is different, except for the OWN bit in the flags field.
> Field
"The format written by HW is different, except for the OWN bit in the
flags field."
This sentence is confusing. Different how? If it's written by HW,
isn't it read by driver? Hence it's this format? What is this "Read
Format" naming convention?
> + * naming assumes SW places uses single buffer per descriptor, rather than
> + * separate header/payload buffers, such that a single 64-bit pointer is
> used.
This sentence is also odd. Is this copied from a data sheet that was
processed through Google translate?
> + */
> +struct eqos_tx_desc {
> + u32 buf_lo;
> + u32 buf_hi;
> + u32 length;
> + u32 flags;
> +};
> +
> +/*
> + * This represents the "Receive Normal Descriptor (Read Format). The format
> + * written by HW is different, except for the OWN bit in the flags field.
> Field
> + * naming assumes SW places uses single buffer per descriptor, rather than
> + * separate header/payload buffers, such that a single 64-bit pointer is
> used.
> + */
> +struct eqos_rx_desc {
> + u32 buf_lo;
> + u32 buf_hi;
> + u32 unused;
> + u32 flags;
> +};
snip...
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[U-Boot] [PATCH V2 2/2] net: add driver for Synopsys Ethernet QoS device
From: Stephen Warren This driver supports the Synopsys Designware Ethernet QoS (Quality of Service) a/k/a eqos IP block, which is a different design than the HW supported by the existing designware.c driver. The IP supports many options for bus type, clocking/reset structure, and feature list. This driver currently supports the specific configuration used in NVIDIA's Tegra186 chip, but should be extensible to other combinations quite easily, as explained in the source. Signed-off-by: Stephen Warren Reviewed-by: Simon Glass # V1 --- v2: * Add note about x86 IO coherency. * Use wait_bit() where possible. * Use a struct definition of the RX and TX descriptors. --- drivers/net/Kconfig | 11 + drivers/net/Makefile |1 + drivers/net/dwc_eth_qos.c | 1497 + 3 files changed, 1509 insertions(+) create mode 100644 drivers/net/dwc_eth_qos.c diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 302c005aa132..d18295a28655 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -64,6 +64,17 @@ config ALTERA_TSE Please find details on the "Triple-Speed Ethernet MegaCore Function Resource Center" of Altera. +config DWC_ETH_QOS + bool "Synopsys DWC Ethernet QOS device support" + depends on DM_ETH + select PHYLIB + help + This driver supports the Synopsys Designware Ethernet QOS (Quality + Of Service) IP block. The IP supports many options for bus type, + clocking/reset structure, and feature list. This driver currently + supports the specific configuration used in NVIDIA's Tegra186 chip, + but should be extensible to other combinations quite easily. + config E1000 bool "Intel PRO/1000 Gigabit Ethernet support" help diff --git a/drivers/net/Makefile b/drivers/net/Makefile index a4485266d457..9a7bfc6d5b05 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -76,3 +76,4 @@ obj-$(CONFIG_FSL_MC_ENET) += ldpaa_eth/ obj-$(CONFIG_FSL_MEMAC) += fm/memac_phy.o obj-$(CONFIG_VSC9953) += vsc9953.o obj-$(CONFIG_PIC32_ETH) += pic32_mdio.o pic32_eth.o +obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c new file mode 100644 index ..f41aba97a494 --- /dev/null +++ b/drivers/net/dwc_eth_qos.c @@ -0,0 +1,1497 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + * + * Portions based on U-Boot's rtl8169.c. + */ + +/* + * This driver supports the Synopsys Designware Ethernet QOS (Quality Of + * Service) IP block. The IP supports multiple options for bus type, clocking/ + * reset structure, and feature list. This driver currently supports the + * specific configuration used in NVIDIA's Tegra186 chip. + * + * The driver is written such that generic core logic is kept separate from + * configuration-specific logic. Code that interacts with configuration- + * specific resources is split out into separate functions to avoid polluting + * common code. If/when this driver is enhanced to support multiple + * configurations, the core code should be adapted to call all configuration- + * specific functions through function pointers, with the definition of those + * function pointers being supplied by struct udevice_id eqos_ids[]'s .data + * field. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Core registers */ + +#define EQOS_MAC_CONFIGURATION 0 +#define EQOS_MAC_CONFIGURATION_GPSLCE BIT(23) +#define EQOS_MAC_CONFIGURATION_CST BIT(21) +#define EQOS_MAC_CONFIGURATION_ACS BIT(20) +#define EQOS_MAC_CONFIGURATION_WD BIT(19) +#define EQOS_MAC_CONFIGURATION_JD BIT(17) +#define EQOS_MAC_CONFIGURATION_JE BIT(16) +#define EQOS_MAC_CONFIGURATION_PS BIT(15) +#define EQOS_MAC_CONFIGURATION_FES BIT(14) +#define EQOS_MAC_CONFIGURATION_DM BIT(13) +#define EQOS_MAC_CONFIGURATION_TE BIT(1) +#define EQOS_MAC_CONFIGURATION_RE BIT(0) + +#define EQOS_MAC_Q0_TX_FLOW_CTRL 0x70 +#define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16 +#define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_MASK 0x +#define EQOS_MAC_Q0_TX_FLOW_CTRL_TFE BIT(1) + +#define EQOS_MAC_RX_FLOW_CTRL 0x90 +#define EQOS_MAC_RX_FLOW_CTRL_RFE BIT(0) + +#define EQOS_MAC_TXQ_PRTY_MAP0 0x98 +#define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT 0 +#define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK 0xff + +#define EQOS_MAC_RXQ_CTRL0 0xa0 +#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT0 +#define EQOS_
