Re: [U-Boot] [PATCH V2 3/4] ARM: AM33xx: Move s_init to a common place
On 23/08/13 11:55, Mark Jackson wrote:
On 23/08/13 11:25, Lokesh Vutla wrote:
Hi Mark,
On Friday 23 August 2013 02:58 PM, Mark Jackson wrote:
On 30/07/13 06:18, Lokesh Vutla wrote:
From: Heiko Schocher h...@denx.de
s_init has the same outline for all the AM33xx based
board. So making it generic.
This also helps in addition of new Soc with minimal changes.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: Heiko Schocher h...@denx.de
Signed-off-by: Tom Rini tr...@ti.com
snip
But this fails to boot. However, if I use the old ASM code:-
void enable_norboot_pin_mux(void)
{
asm(stmfd sp!, {r2 - r4});
asm(movw r4, #0x8A4);
asm(movw r3, #0x44E1);
asm(orrr4, r4, r3, lsl #16);
asm(movr2, #9);
asm(movr3, #8);
asm(gpmc_mux: str r2, [r4], #4);
asm(subs r3, r3, #1);
asm(bnegpmc_mux);
asm(ldmfd sp!, {r2 - r4});
}
This code writes 0x9 into 8 continuous registers starting from
0x44e108a4, this is what done in module_pin_mux norboot_pin_mux
except that it has 9 registers(i guess 9th register was added by mistake..:(
)
Correct me if I am wrong.
Not sure about the code, but it was introduced here:-
http://git.denx.de/?p=u-boot/u-boot-ti.git;a=commit;h=c5c7a7c32d552592ac49749e5c184c89bd50c098
So you are telling this is wrong but boots properly ?
Basically ... yes !!
Is there any update on this issue ?
I'm keen to get our board support files pushed through.
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Re: [U-Boot] [PATCH V2 3/4] ARM: AM33xx: Move s_init to a common place
On 30/07/13 06:18, Lokesh Vutla wrote:
From: Heiko Schocher h...@denx.de
s_init has the same outline for all the AM33xx based
board. So making it generic.
This also helps in addition of new Soc with minimal changes.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: Heiko Schocher h...@denx.de
Signed-off-by: Tom Rini tr...@ti.com
snip
This patch introduces the following new function call ...
+void s_init(void)
+{
+ /*
+ * The ROM will only have set up sufficient pinmux to allow for the
+ * first 4KiB NOR to be read, we must finish doing what we know of
+ * the NOR mux in this space in order to continue.
+ */
+#ifdef CONFIG_NOR_BOOT
+ enable_norboot_pin_mux();
+#endif
... which replaces the old code ...
- /*
- * The ROM will only have set up sufficient pinmux to allow for the
- * first 4KiB NOR to be read, we must finish doing what we know of
- * the NOR mux in this space in order to continue.
- */
-#ifdef CONFIG_NOR_BOOT
- asm(stmfd sp!, {r2 - r4});
- asm(movw r4, #0x8A4);
- asm(movw r3, #0x44E1);
- asm(orrr4, r4, r3, lsl #16);
- asm(movr2, #9);
- asm(movr3, #8);
- asm(gpmc_mux: str r2, [r4], #4);
- asm(subs r3, r3, #1);
- asm(bnegpmc_mux);
- asm(ldmfd sp!, {r2 - r4});
-#endif
Now (for the TI boards) enable_norboot_pin_mux() is defined as:-
+#if defined(CONFIG_NOR_BOOT)
+static struct module_pin_mux norboot_pin_mux[] = {
+ {OFFSET(lcd_data1), MODE(1) | PULLUDDIS},
+ {OFFSET(lcd_data2), MODE(1) | PULLUDDIS},
+ {OFFSET(lcd_data3), MODE(1) | PULLUDDIS},
+ {OFFSET(lcd_data4), MODE(1) | PULLUDDIS},
+ {OFFSET(lcd_data5), MODE(1) | PULLUDDIS},
+ {OFFSET(lcd_data6), MODE(1) | PULLUDDIS},
+ {OFFSET(lcd_data7), MODE(1) | PULLUDDIS},
+ {OFFSET(lcd_data8), MODE(1) | PULLUDDIS},
+ {OFFSET(lcd_data9), MODE(1) | PULLUDDIS},
+ {-1},
+};
+
+void enable_norboot_pin_mux(void)
+{
+ configure_module_pin_mux(norboot_pin_mux);
+}
+#endif
Firstly, this pinmux code seems wrong, since lcd_data pin map:-
lcd_data1 (mode 1) = gpmc_a1_mux1
lcd_data2 (mode 1) = gpmc_a2_mux1
lcd_data3 (mode 1) = gpmc_a3_mux1
lcd_data4 (mode 1) = gpmc_a4_mux1
lcd_data5 (mode 1) = gpmc_a5_mux1
lcd_data6 (mode 1) = gpmc_a6_mux1
lcd_data7 (mode 1) = gpmc_a7_mux1
lcd_data8 (mode 1) = gpmc_a12_mux1
lcd_data9 (mode 1) = gpmc_a13_mux1
Doesn't this leave gpmc_a[8..11] unconfigured ?
Shouldn't we configure lcd_vsync, lcd_hsync and lcd_pclk ?
Secondly, I've modded our Nanobone code to match this new setup, as follows:-
static struct module_pin_mux norboot_pin_mux[] = {
{OFFSET(lcd_data1), (MODE(1) | PULLUDDIS)}, /* GPMC A17 */
{OFFSET(lcd_data2), (MODE(1) | PULLUDDIS)}, /* GPMC A18 */
{OFFSET(lcd_data3), (MODE(1) | PULLUDDIS)}, /* GPMC A19 */
{OFFSET(lcd_data4), (MODE(1) | PULLUDDIS)}, /* GPMC A20 */
{OFFSET(lcd_data5), (MODE(1) | PULLUDDIS)}, /* GPMC A21 */
{OFFSET(lcd_data6), (MODE(1) | PULLUDDIS)}, /* GPMC A22 */
{OFFSET(lcd_data7), (MODE(1) | PULLUDDIS)}, /* GPMC A23 */
{OFFSET(lcd_vsync), (MODE(1) | PULLUDDIS)}, /* GPMC A24 */
{OFFSET(lcd_hsync), (MODE(1) | PULLUDDIS)}, /* GPMC A25 */
{OFFSET(lcd_pclk), (MODE(1) | PULLUDDIS)}, /* GPMC A26 */
{-1},
};
void enable_norboot_pin_mux(void)
{
configure_module_pin_mux(norboot_pin_mux);
}
But this fails to boot. However, if I use the old ASM code:-
void enable_norboot_pin_mux(void)
{
asm(stmfd sp!, {r2 - r4});
asm(movw r4, #0x8A4);
asm(movw r3, #0x44E1);
asm(orrr4, r4, r3, lsl #16);
asm(movr2, #9);
asm(movr3, #8);
asm(gpmc_mux: str r2, [r4], #4);
asm(subs r3, r3, #1);
asm(bnegpmc_mux);
asm(ldmfd sp!, {r2 - r4});
}
... this now boots correctly !!
Anyone care to comment ?
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Re: [U-Boot] [PATCH V2 3/4] ARM: AM33xx: Move s_init to a common place
Hi Mark,
On Friday 23 August 2013 02:58 PM, Mark Jackson wrote:
On 30/07/13 06:18, Lokesh Vutla wrote:
From: Heiko Schocher h...@denx.de
s_init has the same outline for all the AM33xx based
board. So making it generic.
This also helps in addition of new Soc with minimal changes.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: Heiko Schocher h...@denx.de
Signed-off-by: Tom Rini tr...@ti.com
snip
This patch introduces the following new function call ...
+void s_init(void)
+{
+/*
+ * The ROM will only have set up sufficient pinmux to allow for the
+ * first 4KiB NOR to be read, we must finish doing what we know of
+ * the NOR mux in this space in order to continue.
+ */
+#ifdef CONFIG_NOR_BOOT
+enable_norboot_pin_mux();
+#endif
... which replaces the old code ...
-/*
- * The ROM will only have set up sufficient pinmux to allow for the
- * first 4KiB NOR to be read, we must finish doing what we know of
- * the NOR mux in this space in order to continue.
- */
-#ifdef CONFIG_NOR_BOOT
-asm(stmfd sp!, {r2 - r4});
-asm(movw r4, #0x8A4);
-asm(movw r3, #0x44E1);
-asm(orrr4, r4, r3, lsl #16);
-asm(movr2, #9);
-asm(movr3, #8);
-asm(gpmc_mux: str r2, [r4], #4);
-asm(subs r3, r3, #1);
-asm(bnegpmc_mux);
-asm(ldmfd sp!, {r2 - r4});
-#endif
Now (for the TI boards) enable_norboot_pin_mux() is defined as:-
+#if defined(CONFIG_NOR_BOOT)
+static struct module_pin_mux norboot_pin_mux[] = {
+{OFFSET(lcd_data1), MODE(1) | PULLUDDIS},
+{OFFSET(lcd_data2), MODE(1) | PULLUDDIS},
+{OFFSET(lcd_data3), MODE(1) | PULLUDDIS},
+{OFFSET(lcd_data4), MODE(1) | PULLUDDIS},
+{OFFSET(lcd_data5), MODE(1) | PULLUDDIS},
+{OFFSET(lcd_data6), MODE(1) | PULLUDDIS},
+{OFFSET(lcd_data7), MODE(1) | PULLUDDIS},
+{OFFSET(lcd_data8), MODE(1) | PULLUDDIS},
+{OFFSET(lcd_data9), MODE(1) | PULLUDDIS},
+{-1},
+};
Is this configuration not working for you?
+
+void enable_norboot_pin_mux(void)
+{
+configure_module_pin_mux(norboot_pin_mux);
+}
+#endif
Firstly, this pinmux code seems wrong, since lcd_data pin map:-
lcd_data1 (mode 1) = gpmc_a1_mux1
lcd_data2 (mode 1) = gpmc_a2_mux1
lcd_data3 (mode 1) = gpmc_a3_mux1
lcd_data4 (mode 1) = gpmc_a4_mux1
lcd_data5 (mode 1) = gpmc_a5_mux1
lcd_data6 (mode 1) = gpmc_a6_mux1
lcd_data7 (mode 1) = gpmc_a7_mux1
lcd_data8 (mode 1) = gpmc_a12_mux1
lcd_data9 (mode 1) = gpmc_a13_mux1
Doesn't this leave gpmc_a[8..11] unconfigured ?
Shouldn't we configure lcd_vsync, lcd_hsync and lcd_pclk ?
Secondly, I've modded our Nanobone code to match this new setup, as follows:-
static struct module_pin_mux norboot_pin_mux[] = {
{OFFSET(lcd_data1), (MODE(1) | PULLUDDIS)}, /* GPMC A17 */
{OFFSET(lcd_data2), (MODE(1) | PULLUDDIS)}, /* GPMC A18 */
{OFFSET(lcd_data3), (MODE(1) | PULLUDDIS)}, /* GPMC A19 */
{OFFSET(lcd_data4), (MODE(1) | PULLUDDIS)}, /* GPMC A20 */
{OFFSET(lcd_data5), (MODE(1) | PULLUDDIS)}, /* GPMC A21 */
{OFFSET(lcd_data6), (MODE(1) | PULLUDDIS)}, /* GPMC A22 */
{OFFSET(lcd_data7), (MODE(1) | PULLUDDIS)}, /* GPMC A23 */
{OFFSET(lcd_vsync), (MODE(1) | PULLUDDIS)}, /* GPMC A24 */
{OFFSET(lcd_hsync), (MODE(1) | PULLUDDIS)}, /* GPMC A25 */
{OFFSET(lcd_pclk), (MODE(1) | PULLUDDIS)}, /* GPMC A26 */
{-1},
};
void enable_norboot_pin_mux(void)
{
configure_module_pin_mux(norboot_pin_mux);
}
But this fails to boot. However, if I use the old ASM code:-
void enable_norboot_pin_mux(void)
{
asm(stmfd sp!, {r2 - r4});
asm(movw r4, #0x8A4);
asm(movw r3, #0x44E1);
asm(orrr4, r4, r3, lsl #16);
asm(movr2, #9);
asm(movr3, #8);
asm(gpmc_mux: str r2, [r4], #4);
asm(subs r3, r3, #1);
asm(bnegpmc_mux);
asm(ldmfd sp!, {r2 - r4});
}
This code writes 0x9 into 8 continuous registers starting from
0x44e108a4, this is what done in module_pin_mux norboot_pin_mux
except that it has 9 registers(i guess 9th register was added by mistake..:( )
Correct me if I am wrong.
So you are telling this is wrong but boots properly ?
Steve in CC can comment more on this configuration.
Thanks and regards,
Lokesh
... this now boots correctly !!
Anyone care to comment ?
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Re: [U-Boot] [PATCH V2 3/4] ARM: AM33xx: Move s_init to a common place
On 23/08/13 11:25, Lokesh Vutla wrote:
Hi Mark,
On Friday 23 August 2013 02:58 PM, Mark Jackson wrote:
On 30/07/13 06:18, Lokesh Vutla wrote:
From: Heiko Schocher h...@denx.de
s_init has the same outline for all the AM33xx based
board. So making it generic.
This also helps in addition of new Soc with minimal changes.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: Heiko Schocher h...@denx.de
Signed-off-by: Tom Rini tr...@ti.com
snip
But this fails to boot. However, if I use the old ASM code:-
void enable_norboot_pin_mux(void)
{
asm(stmfd sp!, {r2 - r4});
asm(movw r4, #0x8A4);
asm(movw r3, #0x44E1);
asm(orrr4, r4, r3, lsl #16);
asm(movr2, #9);
asm(movr3, #8);
asm(gpmc_mux: str r2, [r4], #4);
asm(subs r3, r3, #1);
asm(bnegpmc_mux);
asm(ldmfd sp!, {r2 - r4});
}
This code writes 0x9 into 8 continuous registers starting from
0x44e108a4, this is what done in module_pin_mux norboot_pin_mux
except that it has 9 registers(i guess 9th register was added by mistake..:( )
Correct me if I am wrong.
Not sure about the code, but it was introduced here:-
http://git.denx.de/?p=u-boot/u-boot-ti.git;a=commit;h=c5c7a7c32d552592ac49749e5c184c89bd50c098
So you are telling this is wrong but boots properly ?
Basically ... yes !!
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Re: [U-Boot] [PATCH V2 3/4] ARM: AM33xx: Move s_init to a common place
On 30/07/13 08:34, Heiko Schocher wrote: Hello Lokesh, Am 30.07.2013 07:18, schrieb Lokesh Vutla: From: Heiko Schocherh...@denx.de s_init has the same outline for all the AM33xx based board. So making it generic. This also helps in addition of new Soc with minimal changes. There's a new function now defined ... void enable_norboot_pin_mux(void) ... but our board *always* boots via NOR. All the required pinmux config is handled by enable_board_pin_mux(). Should I just define this an empty function ? Or should it be a maybe unused function ? Mark J. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 3/4] ARM: AM33xx: Move s_init to a common place
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 08/21/2013 11:51 AM, Mark Jackson wrote: On 30/07/13 08:34, Heiko Schocher wrote: Hello Lokesh, Am 30.07.2013 07:18, schrieb Lokesh Vutla: From: Heiko Schocherh...@denx.de s_init has the same outline for all the AM33xx based board. So making it generic. This also helps in addition of new Soc with minimal changes. There's a new function now defined ... void enable_norboot_pin_mux(void) ... but our board *always* boots via NOR. All the required OK, then you should rip out the SPL bits, yes? Or do you support SD too? :) pinmux config is handled by enable_board_pin_mux(). Should I just define this an empty function ? Or should it be a maybe unused function ? Well, why can't it still be done in that function? - -- Tom -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQIcBAEBAgAGBQJSFOo4AAoJENk4IS6UOR1WZ+wQAJRjGVg/7dygiaJZmtuyHm7D 9uyQJU0o/xrQu3A3i+GBOuYP7D6awCLBCVyTDgTibWcXtvKtHsVwFSc4oDhgVRKl YU5fuO8qVYyCBRiS9QsEOFIPAgubBWg6PWgdCG9pakveNRJ9hWQLsjusePrObGyn pxhFSB4zx6KFuGBufzC+fLzPcM9hY9Xxuiqbj7qvK/oO/k8vdekOWrHE4+y2UBxS LsFzGWlHpN3h5iZwVk+EgrClKK+f4V5MNxyzW8dMGKF42Vl9KVaG7krXl4pUs4ju SoYIxfJ/r8DZjfFi1IuKMacKER1eROTdhGCZl0PtlL4VRxomSNix/gne3gG0ykB6 lGZuv9C046gpkQWQW90+t1IQIDWTOMkEadJ3cVUBZqraIk3bcybLk0pOoaah7ayC bmknCM7hVB+V7HfPGG6U20nhy5R2SebBIt5VdH4xIP5SFMpgcWKCXf9fbjWVwH3v ptnqYIlXgUBoDzA3u3UuaI91i4bsFmnjZfvbKeC4zHXK8uhwow06mU2hMaotGeEg qpki2Ga1CevKddDPJSwzOUyFIo6Tp8HhD//u2EXMEf1jB880fKdSsHbt2URYmxYb 0HmvPFMCP04AOrgmADq3K1Yd4DbxejaWyORdF7rWvAl/lUSElnzo4Q/1DS2LjHOe Ngcvd53zCmpV/51VpbQq =gAOw -END PGP SIGNATURE- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 3/4] ARM: AM33xx: Move s_init to a common place
Hello Lokesh, Am 30.07.2013 07:18, schrieb Lokesh Vutla: From: Heiko Schocherh...@denx.de s_init has the same outline for all the AM33xx based board. So making it generic. This also helps in addition of new Soc with minimal changes. Signed-off-by: Lokesh Vutlalokeshvu...@ti.com Signed-off-by: Heiko Schocherh...@denx.de Signed-off-by: Tom Rinitr...@ti.com --- arch/arm/cpu/armv7/am33xx/board.c| 62 +++-- arch/arm/cpu/armv7/am33xx/clock_ti814x.c |6 ++ arch/arm/include/asm/arch-am33xx/clocks_am33xx.h |6 +- arch/arm/include/asm/arch-am33xx/sys_proto.h |8 ++- board/isee/igep0033/board.c | 50 +++--- board/phytec/pcm051/board.c | 48 +++-- board/ti/am335x/board.c | 80 -- board/ti/am335x/mux.c| 19 + board/ti/ti814x/evm.c| 67 +++--- 9 files changed, 128 insertions(+), 218 deletions(-) Tested-by: Heiko Schocher h...@denx.de Acked-by: Heiko Schocher h...@denx.de Thanks! bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 3/4] ARM: AM33xx: Move s_init to a common place
From: Heiko Schocher h...@denx.de
s_init has the same outline for all the AM33xx based
board. So making it generic.
This also helps in addition of new Soc with minimal changes.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: Heiko Schocher h...@denx.de
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/am33xx/board.c| 62 +++--
arch/arm/cpu/armv7/am33xx/clock_ti814x.c |6 ++
arch/arm/include/asm/arch-am33xx/clocks_am33xx.h |6 +-
arch/arm/include/asm/arch-am33xx/sys_proto.h |8 ++-
board/isee/igep0033/board.c | 50 +++---
board/phytec/pcm051/board.c | 48 +++--
board/ti/am335x/board.c | 80 --
board/ti/am335x/mux.c| 19 +
board/ti/ti814x/evm.c| 67 +++---
9 files changed, 128 insertions(+), 218 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/board.c
b/arch/arm/cpu/armv7/am33xx/board.c
index 64a3af7..2ea3d69 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -137,7 +137,7 @@ int arch_misc_init(void)
}
#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
-void rtc32k_enable(void)
+static void rtc32k_enable(void)
{
struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
@@ -153,11 +153,7 @@ void rtc32k_enable(void)
writel((1 3) | (1 6), rtc-osc);
}
-#define UART_RESET (0x1 1)
-#define UART_CLK_RUNNING_MASK 0x1
-#define UART_SMART_IDLE_EN (0x1 0x3)
-
-void uart_soft_reset(void)
+static void uart_soft_reset(void)
{
struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
u32 regval;
@@ -174,4 +170,58 @@ void uart_soft_reset(void)
regval |= UART_SMART_IDLE_EN;
writel(regval, uart_base-uartsyscfg);
}
+
+static void watchdog_disable(void)
+{
+ struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+
+ writel(0x, wdtimer-wdtwspr);
+ while (readl(wdtimer-wdtwwps) != 0x0)
+ ;
+ writel(0x, wdtimer-wdtwspr);
+ while (readl(wdtimer-wdtwwps) != 0x0)
+ ;
+}
#endif
+
+void s_init(void)
+{
+ /*
+* The ROM will only have set up sufficient pinmux to allow for the
+* first 4KiB NOR to be read, we must finish doing what we know of
+* the NOR mux in this space in order to continue.
+*/
+#ifdef CONFIG_NOR_BOOT
+ enable_norboot_pin_mux();
+#endif
+ /*
+* Save the boot parameters passed from romcode.
+* We cannot delay the saving further than this,
+* to prevent overwrites.
+*/
+#ifdef CONFIG_SPL_BUILD
+ save_omap_boot_params();
+#endif
+#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
+ watchdog_disable();
+ timer_init();
+ set_uart_mux_conf();
+ setup_clocks_for_console();
+ uart_soft_reset();
+#endif
+#ifdef CONFIG_NOR_BOOT
+ gd-baudrate = CONFIG_BAUDRATE;
+ serial_init();
+ gd-have_console = 1;
+#else
+ gd = gdata;
+ preloader_console_init();
+#endif
+#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
+ prcm_init();
+ set_mux_conf_regs();
+ /* Enable RTC32K clock */
+ rtc32k_enable();
+ sdram_init();
+#endif
+}
diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
index 965e875..93c7f7b 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
@@ -277,6 +277,12 @@ static void enable_per_clocks(void)
writel(PRCM_MOD_EN, cmalwon-ethernet1clkctrl);
while ((readl(cmalwon-ethernet1clkctrl) ENET_CLKCTRL_CMPL) != 0)
;
+
+ /* RTC clocks */
+ writel(PRCM_MOD_EN, cmalwon-rtcclkstctrl);
+ writel(PRCM_MOD_EN, cmalwon-rtcclkctrl);
+ while (readl(cmalwon-rtcclkctrl) != PRCM_MOD_EN)
+ ;
}
/*
diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
index 80e1899..140379f 100644
--- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
+++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
@@ -16,8 +16,10 @@
#define CONFIG_SYS_MPUCLK 550
#endif
-extern void pll_init(void);
-extern void enable_emif_clocks(void);
+#define UART_RESET (0x1 1)
+#define UART_CLK_RUNNING_MASK 0x1
+#define UART_SMART_IDLE_EN (0x1 0x3)
+
extern void enable_dmm_clocks(void);
#endif /* endif _CLOCKS_AM33XX_H_ */
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h
b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index dbcede0..c6070a3 100644
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -35,7 +35,11 @@ void enable_gpmc_cs_config(const u32 *gpmc_config, struct
gpmc_cs *cs, u32 base,
u32
