Re: [U-Boot] [PATCH V4 2/4] ARM: arm1176: enable instruction cache in arch_cpu_init()

[Simon Glass]

On Sun, Aug 5, 2012 at 7:07 PM, Stephen Warren swar...@wwwdotorg.org wrote:
 Note that this affects all users of the ARM1176 CPU that enable
 CONFIG_ARCH_CPU_INIT, not just the BCM2835 SoC, potentially such as
 tnetv107x.

 Cc: Cyril Chemparathy cy...@ti.com
 Signed-off-by: Stephen Warren swar...@wwwdotorg.org

Acked-by: Simon Glass s...@chromium.org

 ---
 v4: No change
 v3: No change, re-ordered patch
 v2: No change
 ---
  arch/arm/cpu/arm1176/cpu.c |7 +++
  1 file changed, 7 insertions(+)

 diff --git a/arch/arm/cpu/arm1176/cpu.c b/arch/arm/cpu/arm1176/cpu.c
 index c0fd114..532a90b 100644
 --- a/arch/arm/cpu/arm1176/cpu.c
 +++ b/arch/arm/cpu/arm1176/cpu.c
 @@ -65,3 +65,10 @@ static void cache_flush (void)
 /* mem barrier to sync things */
 asm (mcr p15, 0, %0, c7, c10, 4: :r (0));
  }
 +
 +int arch_cpu_init(void)
 +{
 +   icache_enable();
 +
 +   return 0;
 +}
 --
 1.7.9.5

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[U-Boot] [PATCH V4 2/4] ARM: arm1176: enable instruction cache in arch_cpu_init()

[Stephen Warren]

Note that this affects all users of the ARM1176 CPU that enable
CONFIG_ARCH_CPU_INIT, not just the BCM2835 SoC, potentially such as
tnetv107x.

Cc: Cyril Chemparathy cy...@ti.com
Signed-off-by: Stephen Warren swar...@wwwdotorg.org
---
v4: No change
v3: No change, re-ordered patch
v2: No change
---
 arch/arm/cpu/arm1176/cpu.c |7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/cpu/arm1176/cpu.c b/arch/arm/cpu/arm1176/cpu.c
index c0fd114..532a90b 100644
--- a/arch/arm/cpu/arm1176/cpu.c
+++ b/arch/arm/cpu/arm1176/cpu.c
@@ -65,3 +65,10 @@ static void cache_flush (void)
/* mem barrier to sync things */
asm (mcr p15, 0, %0, c7, c10, 4: :r (0));
 }
+
+int arch_cpu_init(void)
+{
+   icache_enable();
+
+   return 0;
+}
-- 
1.7.9.5

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