Re: [U-Boot] [PATCH V4 2/5] ARM: Add Support for Marvell Pantheon Familiy SoCs

2011-01-18 Thread Wolfgang Denk 
Dear Lei Wen,

In message <1294754710-7834-3-git-send-email-lei...@marvell.com> you wrote:
> Pantheon Family processors are highly integrated SoCs
> based on Sheeva_88SV331x-v5 PJ1 cpu core.
> Ref:
> http://www.marvell.com/products/processors/communications/marvell_pantheon_910_920_pb.pdf
...
> +/* For preventing risk of instability in reading counter value,
> + * first set read request to register cvwr and then read same
> + * register after it captures counter value.
> + */

Incorrect multiline comment style.  Please fix globally.

> +ulong read_timer(void)
> +{
> + struct panthtmr_registers *panthtimers =
> + (struct panthtmr_registers *) PANTHEON_TIMER_BASE;
> + volatile int loop=100;
> +
> + writel(COUNT_RD_REQ, &panthtimers->cvwr);
> + while (loop--);

Please write this as

while (loop--)
;

Please fix globally.


Best regards,

Wolfgang Denk

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[U-Boot] [PATCH V4 2/5] ARM: Add Support for Marvell Pantheon Familiy SoCs

2011-01-11 Thread Lei Wen 
Pantheon Family processors are highly integrated SoCs
based on Sheeva_88SV331x-v5 PJ1 cpu core.
Ref:
http://www.marvell.com/products/processors/communications/marvell_pantheon_910_920_pb.pdf

SoC versions Supported:
1) PANTHEON920  (TD)
2) PANTHEON910  (TTC)

Signed-off-by: Lei Wen 
---
V2:

V3:
Fix copyright claim year.

V4:
Add change log to each patch.

 arch/arm/cpu/arm926ejs/pantheon/Makefile  |   46 ++
 arch/arm/cpu/arm926ejs/pantheon/cpu.c |   78 ++
 arch/arm/cpu/arm926ejs/pantheon/dram.c|  130 
 arch/arm/cpu/arm926ejs/pantheon/timer.c   |  204 +
 arch/arm/include/asm/arch-pantheon/config.h   |   44 ++
 arch/arm/include/asm/arch-pantheon/cpu.h  |   79 ++
 arch/arm/include/asm/arch-pantheon/pantheon.h |   54 +++
 7 files changed, 635 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/cpu/arm926ejs/pantheon/Makefile
 create mode 100644 arch/arm/cpu/arm926ejs/pantheon/cpu.c
 create mode 100644 arch/arm/cpu/arm926ejs/pantheon/dram.c
 create mode 100644 arch/arm/cpu/arm926ejs/pantheon/timer.c
 create mode 100644 arch/arm/include/asm/arch-pantheon/config.h
 create mode 100644 arch/arm/include/asm/arch-pantheon/cpu.h
 create mode 100644 arch/arm/include/asm/arch-pantheon/pantheon.h

diff --git a/arch/arm/cpu/arm926ejs/pantheon/Makefile 
b/arch/arm/cpu/arm926ejs/pantheon/Makefile
new file mode 100644
index 000..ab94985
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/pantheon/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2011
+# Marvell Semiconductor 
+# Written-by: Lei Wen 
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(SOC).o
+
+COBJS-y= cpu.o timer.o dram.o
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS   := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all:   $(obj).depend $(LIB)
+
+$(LIB):$(OBJS)
+   $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/arch/arm/cpu/arm926ejs/pantheon/cpu.c 
b/arch/arm/cpu/arm926ejs/pantheon/cpu.c
new file mode 100644
index 000..9ddc77c
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/pantheon/cpu.c
@@ -0,0 +1,78 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor 
+ * Written-by: Lei Wen 
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include 
+#include 
+#include 
+
+#define UARTCLK14745KHZ(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
+#define SET_MRVL_ID(1<<8)
+#define L2C_RAM_SEL(1<<4)
+
+int arch_cpu_init(void)
+{
+   u32 val;
+   struct panthcpu_registers *cpuregs =
+   (struct panthcpu_registers*) PANTHEON_CPU_BASE;
+
+   struct panthapb_registers *apbclkres =
+   (struct panthapb_registers*) PANTHEON_APBC_BASE;
+
+   struct panthmpmu_registers *mpmu =
+   (struct panthmpmu_registers*) PANTHEON_MPMU_BASE;
+
+   /* set SEL_MRVL_ID bit in PANTHEON_CPU_CONF register */
+   val = readl(&cpuregs->cpu_conf);
+   val = val | SET_MRVL_ID;
+   writel(val, &cpuregs->cpu_conf);
+
+   /* Turn on clock gating (PMUM_CCGR) */
+   writel(0x, &mpmu->ccgr);
+
+   /* Turn on clock gating (PMUM_ACGR) */
+   writel(0x, &mpmu->acgr);
+
+   /* Tu