Re: [U-Boot] [PATCH V7 1/3] Initial support for Marvell Orion5x SoC
-Original Message-
From: Albert ARIBAUD [mailto:albert.arib...@free.fr]
Sent: Friday, June 11, 2010 2:03 AM
To: Prafulla Wadaskar
Cc: u-boot@lists.denx.de
Subject: Re: [U-Boot] [PATCH V7 1/3] Initial support for
Marvell Orion5x SoC
Hi Prafulla,
Le 10/06/2010 21:36, Prafulla Wadaskar a écrit :
+/* Display device and revision IDs.
+ * This function must cover all known device/revision
+ * combinations, not only the one for which u-boot is
+ * compiled; this way, one can identify actual HW in
+ * case of a mismatch.
+ */
+ if (dev == MV88F5181_DEV_ID) {
Pls see comments at the end
+ } else if (dev == MV88F6183_DEV_ID) {
Pls see comments at the end
+/*
+ * The following definitions are intended for identifying
+ * the real device and revision on which u-boot is running
+ * even if it was compiled only for a specific one. Thus,
+ * these constants must not be considered chip-specific.
+ */
+
+/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */
+#define MV88F5181_DEV_ID0x5181
+#define MV88F5181_REV_B13
+#define MV88F5181L_REV_A0 8
+#define MV88F5181L_REV_A1 9
+/* Orion-NAS (88F5182) */
+#define MV88F5182_DEV_ID0x5182
+#define MV88F5182_REV_A22
+/* Orion-2 (88F5281) */
+#define MV88F5281_DEV_ID0x5281
+#define MV88F5281_REV_D04
+#define MV88F5281_REV_D15
+#define MV88F5281_REV_D26
+/* Orion-1-90 (88F6183) */
+#define MV88F6183_DEV_ID0x6183
+#define MV88F6183_REV_B03
+
Pls refer comments at the end.
Small request-
As per this definition only 5182 is supported and tested,
It would be more logical to remove 5181 and 6183 specific code,
We can always add it as it is required, at this moment it
looks like
a dead code.
This was raised and discussed before:
http://article.gmane.org/gmane.comp.boot-loaders.u-boot/73579
/match=orion5x+device+revision
For any other purpose than identification of the actual SoC, I would
have agreed about removing anything not related to 5182. But here,
precisely, the code is trying to print the identity of the
*actual* SoC
it is being run on, as opposed to that of the *assumed* SoC it was
compiled for.
Thus here the code must define and test for as many device
and revision
IDs as possible so as to give the most accurate information possible.
This is epxlicitely stated in the comments before the identification
function and the device and revision defines.
also moving 5281 specific code to mv88f5182.h will make this patch
clean and complete.
If you're talking about the device / variant IDs, I don't think they
should move for the reason above; if that's something else,
can you be
more precise?
Rest everything seems to be okay
Ok. If we can agree about the identification function, then
I'll post a
final V8 patch with GPIO/MPP enabled.
Hi Albert
This was my suggestion,
if no one else have any suggestion/objection, we can go ahead with v8 patch as
you planned.
Regards..
Prafulla . .
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Re: [U-Boot] [PATCH V7 1/3] Initial support for Marvell Orion5x SoC
Le 14/06/2010 09:09, Prafulla Wadaskar a écrit : Ok. If we can agree about the identification function, then I'll post a final V8 patch with GPIO/MPP enabled. Hi Albert This was my suggestion, if no one else have any suggestion/objection, we can go ahead with v8 patch as you planned. Regards.. Prafulla . . Thanks Prafulla. Patch V8 to follow, then. :) Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V7 1/3] Initial support for Marvell Orion5x SoC
Hi Albert I am OOO for next four days, I will try to provide feedback earliest possible Regards.. Prafulla . . -Original Message- From: u-boot-boun...@lists.denx.de [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Albert Aribaud Sent: Thursday, June 10, 2010 2:20 AM To: u-boot@lists.denx.de Subject: [U-Boot] [PATCH V7 1/3] Initial support for Marvell Orion5x SoC This patch adds support for the Marvell Orion5x SoC. It has no use alone, and must be followed by a patch to add Orion5x support for serial, then support for the ED Mini V2, an Orion5x-based product from LaCie. Signed-off-by: Albert Aribaud albert.arib...@free.fr --- Patchset history V1: Initial monolithic patch. V2: split in three patches : orion, serial, edmini; checkpatch'ed, with only 6 errors, in patch 1/3, all 6 errors being false positives. V3: useless GPIO and MPP programming support removed; low level init added/CONFIG_SKIP_LOW_LEVEL_INIT removed. V4: all files licensed GPLv2-only removed; RAM bank size detection now uses get_ram_size(). V5: Replaced macros by C structs in dram code. Removed compilation warnings in dram code. Added comments to legacy flash definitions. Split low level init code into SoC- and Chip-specifics. V6: Set copyright dates to 2010, and put standard GPL notice mentioning Marvell's copyright on *_lowlevel_init.S files. V7: Moved GPIO and MPP init code in SoC arch_misc_init() in C. lowlevel_init.S now only contains DRAM init code. Patch 1 checkpatched with 0 errors and 1 spurious warning. Patches 2 and 3 checkpatched with 0 errors and 0 warnings. arch/arm/cpu/arm926ejs/orion5x/Makefile| 55 + arch/arm/cpu/arm926ejs/orion5x/cpu.c | 271 ++ arch/arm/cpu/arm926ejs/orion5x/dram.c | 64 + arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S | 293 arch/arm/cpu/arm926ejs/orion5x/timer.c | 181 +++ arch/arm/include/asm/arch-orion5x/cpu.h| 203 arch/arm/include/asm/arch-orion5x/mv88f5182.h | 40 arch/arm/include/asm/arch-orion5x/orion5x.h| 69 ++ 8 files changed, 1176 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/orion5x/Makefile create mode 100644 arch/arm/cpu/arm926ejs/orion5x/cpu.c create mode 100644 arch/arm/cpu/arm926ejs/orion5x/dram.c create mode 100644 arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S create mode 100644 arch/arm/cpu/arm926ejs/orion5x/timer.c create mode 100644 arch/arm/include/asm/arch-orion5x/cpu.h create mode 100644 arch/arm/include/asm/arch-orion5x/mv88f5182.h create mode 100644 arch/arm/include/asm/arch-orion5x/orion5x.h diff --git a/arch/arm/cpu/arm926ejs/orion5x/Makefile b/arch/arm/cpu/arm926ejs/orion5x/Makefile new file mode 100644 index 000..11f4141 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/orion5x/Makefile @@ -0,0 +1,55 @@ +# +# Copyright (C) 2010 Albert ARIBAUD albert.arib...@free.fr +# +# Based on original Kirkwood support which is +# (C) Copyright 2009 +# Marvell Semiconductor www.marvell.com +# Written-by: Prafulla Wadaskar prafu...@marvell.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS-y = cpu.o +COBJS-y += dram.o +COBJS-y += timer.o + +ifndef CONFIG_SKIP_LOWLEVEL_INIT +SOBJS:= lowlevel_init.o +endif + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/cpu/arm926ejs/orion5x/cpu.c new file mode 100644 index 000..807174a --- /dev/null +++ b/arch/arm/cpu/arm926ejs/orion5x/cpu.c @@ -0,0 +1,271 @@ +/* + * Copyright (C) 2010 Albert ARIBAUD albert.arib...@free.fr
Re: [U-Boot] [PATCH V7 1/3] Initial support for Marvell Orion5x SoC
-Original Message-
From: u-boot-boun...@lists.denx.de
[mailto:u-boot-boun...@lists.denx.de] On Behalf Of Albert Aribaud
Sent: Thursday, June 10, 2010 2:20 AM
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH V7 1/3] Initial support for Marvell
Orion5x SoC
This patch adds support for the Marvell Orion5x SoC.
It has no use alone, and must be followed by a patch
to add Orion5x support for serial, then support for
the ED Mini V2, an Orion5x-based product from LaCie.
Signed-off-by: Albert Aribaud albert.arib...@free.fr
---
...snip...
diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c
b/arch/arm/cpu/arm926ejs/orion5x/cpu.c
new file mode 100644
index 000..807174a
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/orion5x/cpu.c
@@ -0,0 +1,271 @@
+/*
+ * Copyright (C) 2010 Albert ARIBAUD albert.arib...@free.fr
+ *
+ * Based on original Kirkwood support which is
+ * (C) Copyright 2009
+ * Marvell Semiconductor www.marvell.com
+ * Written-by: Prafulla Wadaskar prafu...@marvell.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include common.h
+#include netdev.h
+#include asm/cache.h
+#include u-boot/md5.h
+#include asm/arch/orion5x.h
+#include hush.h
+
+#define BUFLEN 16
+
+void reset_cpu(unsigned long ignored)
+{
+ struct orion5x_cpu_registers *cpureg =
+ (struct orion5x_cpu_registers *)ORION5X_CPU_REG_BASE;
+
+ writel(readl(cpureg-rstoutn_mask) | (1 2),
+ cpureg-rstoutn_mask);
+ writel(readl(cpureg-sys_soft_rst) | 1,
+ cpureg-sys_soft_rst);
+ while (1)
+ ;
+}
+
+/*
+ * Window Size
+ * Used with the Base register to set the address window
size and location.
+ * Must be programmed from LSB to MSB as sequence of ones followed by
+ * sequence of zeros. The number of ones specifies the size
of the window in
+ * 64 KByte granularity (e.g., a value of 0x00FF specifies
256 = 16 MByte).
+ * NOTE: A value of 0x0 specifies 64-KByte size.
+ */
+unsigned int orion5x_winctrl_calcsize(unsigned int sizeval)
+{
+ int i;
+ unsigned int j = 0;
+ u32 val = sizeval 1;
+
+ for (i = 0; val 0x1; i++) {
+ j |= (1 i);
+ val = val 1;
+ }
+ return 0x j;
+}
+
+/*
+ * orion5x_config_adr_windows - Configure address Windows
+ *
+ * There are 8 address windows supported by Orion5x Soc to
addess different
+ * devices. Each window can be configured for size, BAR and
remap addr
+ * Below configuration is standard for most of the cases
+ *
+ * If remap function not used, remap_lo must be set as base
+ *
+ * Reference Documentation:
+ * Mbus-L to Mbus Bridge Registers Configuration.
+ * (Sec 25.1 and 25.3 of Datasheet)
+ */
+int orion5x_config_adr_windows(void)
+{
+ struct orion5x_win_registers *winregs =
+ (struct orion5x_win_registers *)ORION5X_CPU_WIN_BASE;
+
+ /* Window 0: PCIE MEM address space */
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCIE_MEM,
+ ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM,
+ ORION5X_WIN_ENABLE), winregs[0].ctrl);
+ writel(ORION5X_DEFADR_PCIE_MEM, winregs[0].base);
+ writel(ORION5X_DEFADR_PCIE_MEM_REMAP_LO, winregs[0].remap_lo);
+ writel(ORION5X_DEFADR_PCIE_MEM_REMAP_HI, winregs[0].remap_hi);
+
+ /* Window 1: PCIE IO address space */
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCIE_IO,
+ ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO,
+ ORION5X_WIN_ENABLE), winregs[1].ctrl);
+ writel(ORION5X_DEFADR_PCIE_IO, winregs[1].base);
+ writel(ORION5X_DEFADR_PCIE_IO_REMAP_LO, winregs[1].remap_lo);
+ writel(ORION5X_DEFADR_PCIE_IO_REMAP_HI, winregs[1].remap_hi);
+
+ /* Window 2: PCI MEM address space */
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCI_MEM,
+ ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_MEM,
+ ORION5X_WIN_ENABLE), winregs[2].ctrl);
+ writel(ORION5X_DEFADR_PCI_MEM, winregs[2].base);
+
+ /* Window 3: PCI IO address space */
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCI_IO,
+ ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_IO
Re: [U-Boot] [PATCH V7 1/3] Initial support for Marvell Orion5x SoC
-Original Message-
From: u-boot-boun...@lists.denx.de
[mailto:u-boot-boun...@lists.denx.de] On Behalf Of Albert Aribaud
Sent: Thursday, June 10, 2010 2:20 AM
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH V7 1/3] Initial support for Marvell
Orion5x SoC
...snip...
+/*
+ * SOC specific misc init
+ */
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+ u32 temp;
+
+ /*CPU streaming write allocate */
+ temp = readfr_extra_feature_reg();
+ temp = ~(1 28); /* disable wr alloc */
+ writefr_extra_feature_reg(temp);
+
+ temp = readfr_extra_feature_reg();
+ temp = ~(1 29); /* streaming disabled */
+ writefr_extra_feature_reg(temp);
+
+ /* L2Cache settings */
+ temp = readfr_extra_feature_reg();
+ /* Disable L2C pre fetch - Set bit 24 */
+ temp |= (1 24);
+ /* enable L2C - Set bit 22 */
+ temp |= (1 22);
+ writefr_extra_feature_reg(temp);
+
+ icache_enable();
+ /* Change reset vector to address 0x0 */
+ temp = get_cr();
+ set_cr(temp ~CR_V);
+
+ /* Set CPIOs and MPPs - values provided by board
+include file */
+/*
+ writel(ORION5X_MPP_BASE+0x00, ORION5X_MPP0_7);
+ writel(ORION5X_MPP_BASE+0x04, ORION5X_MPP8_15);
+ writel(ORION5X_MPP_BASE+0x50, ORION5X_MPP16_23);
+ writel(ORION5X_GPIO_BASE+0x04, ORION5X_GPIO_OUT_ENABLE);
+*/
Pls remove dead code, I think you need to enable it !!
Regards..
Prafulla . .
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Re: [U-Boot] [PATCH V7 1/3] Initial support for Marvell Orion5x SoC
Hi Prafulla,
Le 10/06/2010 21:36, Prafulla Wadaskar a écrit :
+/* Display device and revision IDs.
+ * This function must cover all known device/revision
+ * combinations, not only the one for which u-boot is
+ * compiled; this way, one can identify actual HW in
+ * case of a mismatch.
+ */
+ if (dev == MV88F5181_DEV_ID) {
Pls see comments at the end
+ } else if (dev == MV88F6183_DEV_ID) {
Pls see comments at the end
+/*
+ * The following definitions are intended for identifying
+ * the real device and revision on which u-boot is running
+ * even if it was compiled only for a specific one. Thus,
+ * these constants must not be considered chip-specific.
+ */
+
+/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */
+#define MV88F5181_DEV_ID0x5181
+#define MV88F5181_REV_B13
+#define MV88F5181L_REV_A0 8
+#define MV88F5181L_REV_A1 9
+/* Orion-NAS (88F5182) */
+#define MV88F5182_DEV_ID0x5182
+#define MV88F5182_REV_A22
+/* Orion-2 (88F5281) */
+#define MV88F5281_DEV_ID0x5281
+#define MV88F5281_REV_D04
+#define MV88F5281_REV_D15
+#define MV88F5281_REV_D26
+/* Orion-1-90 (88F6183) */
+#define MV88F6183_DEV_ID0x6183
+#define MV88F6183_REV_B03
+
Pls refer comments at the end.
Small request-
As per this definition only 5182 is supported and tested,
It would be more logical to remove 5181 and 6183 specific code,
We can always add it as it is required, at this moment it looks like
a dead code.
This was raised and discussed before:
http://article.gmane.org/gmane.comp.boot-loaders.u-boot/73579/match=orion5x+device+revision
For any other purpose than identification of the actual SoC, I would
have agreed about removing anything not related to 5182. But here,
precisely, the code is trying to print the identity of the *actual* SoC
it is being run on, as opposed to that of the *assumed* SoC it was
compiled for.
Thus here the code must define and test for as many device and revision
IDs as possible so as to give the most accurate information possible.
This is epxlicitely stated in the comments before the identification
function and the device and revision defines.
also moving 5281 specific code to mv88f5182.h will make this patch
clean and complete.
If you're talking about the device / variant IDs, I don't think they
should move for the reason above; if that's something else, can you be
more precise?
Rest everything seems to be okay
Ok. If we can agree about the identification function, then I'll post a
final V8 patch with GPIO/MPP enabled.
Regards..
Prafulla . .
Cheers!
Amicalement,
--
Albert.
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[U-Boot] [PATCH V7 1/3] Initial support for Marvell Orion5x SoC
This patch adds support for the Marvell Orion5x SoC. It has no use alone, and must be followed by a patch to add Orion5x support for serial, then support for the ED Mini V2, an Orion5x-based product from LaCie. Signed-off-by: Albert Aribaud albert.arib...@free.fr --- Patchset history V1: Initial monolithic patch. V2: split in three patches : orion, serial, edmini; checkpatch'ed, with only 6 errors, in patch 1/3, all 6 errors being false positives. V3: useless GPIO and MPP programming support removed; low level init added/CONFIG_SKIP_LOW_LEVEL_INIT removed. V4: all files licensed GPLv2-only removed; RAM bank size detection now uses get_ram_size(). V5: Replaced macros by C structs in dram code. Removed compilation warnings in dram code. Added comments to legacy flash definitions. Split low level init code into SoC- and Chip-specifics. V6: Set copyright dates to 2010, and put standard GPL notice mentioning Marvell's copyright on *_lowlevel_init.S files. V7: Moved GPIO and MPP init code in SoC arch_misc_init() in C. lowlevel_init.S now only contains DRAM init code. Patch 1 checkpatched with 0 errors and 1 spurious warning. Patches 2 and 3 checkpatched with 0 errors and 0 warnings. arch/arm/cpu/arm926ejs/orion5x/Makefile| 55 + arch/arm/cpu/arm926ejs/orion5x/cpu.c | 271 ++ arch/arm/cpu/arm926ejs/orion5x/dram.c | 64 + arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S | 293 arch/arm/cpu/arm926ejs/orion5x/timer.c | 181 +++ arch/arm/include/asm/arch-orion5x/cpu.h| 203 arch/arm/include/asm/arch-orion5x/mv88f5182.h | 40 arch/arm/include/asm/arch-orion5x/orion5x.h| 69 ++ 8 files changed, 1176 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/orion5x/Makefile create mode 100644 arch/arm/cpu/arm926ejs/orion5x/cpu.c create mode 100644 arch/arm/cpu/arm926ejs/orion5x/dram.c create mode 100644 arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S create mode 100644 arch/arm/cpu/arm926ejs/orion5x/timer.c create mode 100644 arch/arm/include/asm/arch-orion5x/cpu.h create mode 100644 arch/arm/include/asm/arch-orion5x/mv88f5182.h create mode 100644 arch/arm/include/asm/arch-orion5x/orion5x.h diff --git a/arch/arm/cpu/arm926ejs/orion5x/Makefile b/arch/arm/cpu/arm926ejs/orion5x/Makefile new file mode 100644 index 000..11f4141 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/orion5x/Makefile @@ -0,0 +1,55 @@ +# +# Copyright (C) 2010 Albert ARIBAUD albert.arib...@free.fr +# +# Based on original Kirkwood support which is +# (C) Copyright 2009 +# Marvell Semiconductor www.marvell.com +# Written-by: Prafulla Wadaskar prafu...@marvell.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(SOC).a + +COBJS-y= cpu.o +COBJS-y+= dram.o +COBJS-y+= timer.o + +ifndef CONFIG_SKIP_LOWLEVEL_INIT +SOBJS := lowlevel_init.o +endif + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) + +all: $(obj).depend $(LIB) + +$(LIB):$(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/cpu/arm926ejs/orion5x/cpu.c new file mode 100644 index 000..807174a --- /dev/null +++ b/arch/arm/cpu/arm926ejs/orion5x/cpu.c @@ -0,0 +1,271 @@ +/* + * Copyright (C) 2010 Albert ARIBAUD albert.arib...@free.fr + * + * Based on original Kirkwood support which is + * (C) Copyright 2009 + * Marvell Semiconductor www.marvell.com + * Written-by: Prafulla Wadaskar prafu...@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later
[U-Boot] [PATCH V7 1/3] Initial support for Marvell Orion5x SoC
This patch adds support for the Marvell Orion5x SoC. It has no use alone, and must be followed by a patch to add Orion5x support for serial, then support for the ED Mini V2, an Orion5x-based product from LaCie. Signed-off-by: Albert Aribaud albert.arib...@free.fr --- Patchset history V1: Initial monolithic patch. V2: split in three patches : orion, serial, edmini; checkpatch'ed, with only 6 errors, in patch 1/3, all 6 errors being false positives. V3: useless GPIO and MPP programming support removed; low level init added/CONFIG_SKIP_LOW_LEVEL_INIT removed. V4: all files licensed GPLv2-only removed; RAM bank size detection now uses get_ram_size(). V5: Replaced macros by C structs in dram code. Removed compilation warnings in dram code. Added comments to legacy flash definitions. Split low level init code into SoC- and Chip-specifics. V6: Set copyright dates to 2010, and put standard GPL notice mentioning Marvell's copyright on *_lowlevel_init.S files. V7: Moved GPIO and MPP init code in SoC arch_misc_init() in C. lowlevel_init.S now only contains DRAM init code. Patch 1 checkpatched with 0 errors and 1 spurious warning. Patches 2 and 3 checkpatched with 0 errors and 0 warnings. arch/arm/cpu/arm926ejs/orion5x/Makefile| 55 + arch/arm/cpu/arm926ejs/orion5x/cpu.c | 271 ++ arch/arm/cpu/arm926ejs/orion5x/dram.c | 64 + arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S | 293 arch/arm/cpu/arm926ejs/orion5x/timer.c | 181 +++ arch/arm/include/asm/arch-orion5x/cpu.h| 203 arch/arm/include/asm/arch-orion5x/mv88f5182.h | 40 arch/arm/include/asm/arch-orion5x/orion5x.h| 69 ++ 8 files changed, 1176 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/orion5x/Makefile create mode 100644 arch/arm/cpu/arm926ejs/orion5x/cpu.c create mode 100644 arch/arm/cpu/arm926ejs/orion5x/dram.c create mode 100644 arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S create mode 100644 arch/arm/cpu/arm926ejs/orion5x/timer.c create mode 100644 arch/arm/include/asm/arch-orion5x/cpu.h create mode 100644 arch/arm/include/asm/arch-orion5x/mv88f5182.h create mode 100644 arch/arm/include/asm/arch-orion5x/orion5x.h diff --git a/arch/arm/cpu/arm926ejs/orion5x/Makefile b/arch/arm/cpu/arm926ejs/orion5x/Makefile new file mode 100644 index 000..11f4141 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/orion5x/Makefile @@ -0,0 +1,55 @@ +# +# Copyright (C) 2010 Albert ARIBAUD albert.arib...@free.fr +# +# Based on original Kirkwood support which is +# (C) Copyright 2009 +# Marvell Semiconductor www.marvell.com +# Written-by: Prafulla Wadaskar prafu...@marvell.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(SOC).a + +COBJS-y= cpu.o +COBJS-y+= dram.o +COBJS-y+= timer.o + +ifndef CONFIG_SKIP_LOWLEVEL_INIT +SOBJS := lowlevel_init.o +endif + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) + +all: $(obj).depend $(LIB) + +$(LIB):$(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/cpu/arm926ejs/orion5x/cpu.c new file mode 100644 index 000..807174a --- /dev/null +++ b/arch/arm/cpu/arm926ejs/orion5x/cpu.c @@ -0,0 +1,271 @@ +/* + * Copyright (C) 2010 Albert ARIBAUD albert.arib...@free.fr + * + * Based on original Kirkwood support which is + * (C) Copyright 2009 + * Marvell Semiconductor www.marvell.com + * Written-by: Prafulla Wadaskar prafu...@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later
