Re: [U-Boot] [PATCH v0 4/5] arm: mvebu: Fix ddr3_init() cpu config

[Stefan Roese]

On 28.10.2015 16:44, dirk.eib...@gdsys.cc wrote:

From: Dirk Eibach 

Armada 38x has a maximum of two cores. Probably copy/paste
bug from Armada XP.

Signed-off-by: Dirk Eibach 


Applied to u-boot-marvell/master.

Thanks,
Stefan

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Re: [U-Boot] [PATCH v0 4/5] arm: mvebu: Fix ddr3_init() cpu config

[Dirk Eibach]

Hi Stefan,

2015-10-28 17:35 GMT+01:00 Stefan Roese :
> Hi Dirk,
>
> On 28.10.2015 16:44, dirk.eib...@gdsys.cc wrote:
>>
>> From: Dirk Eibach 
>>
>> Armada 38x has a maximum of two cores. Probably copy/paste
>> bug from Armada XP.
>>
>> Signed-off-by: Dirk Eibach 
>> ---
>>
>>   drivers/ddr/marvell/a38x/ddr3_init.c | 2 --
>>   1 file changed, 2 deletions(-)
>>
>> diff --git a/drivers/ddr/marvell/a38x/ddr3_init.c
>> b/drivers/ddr/marvell/a38x/ddr3_init.c
>> index d6ed8e0..cbfc58c 100644
>> --- a/drivers/ddr/marvell/a38x/ddr3_init.c
>> +++ b/drivers/ddr/marvell/a38x/ddr3_init.c
>> @@ -306,8 +306,6 @@ int ddr3_init(void)
>> SAR1_CPU_CORE_OFFSET;
>> switch (soc_num) {
>> case 0x3:
>> -   reg_bit_set(CPU_CONFIGURATION_REG(3), CPU_MRVL_ID_OFFSET);
>> -   reg_bit_set(CPU_CONFIGURATION_REG(2), CPU_MRVL_ID_OFFSET);
>> case 0x1:
>> reg_bit_set(CPU_CONFIGURATION_REG(1), CPU_MRVL_ID_OFFSET);
>> case 0x0:
>
>
> Shouldn't you remove the "case 0x3:" line as well?

Nope, according to Reset Configuration Pins table in the hardware spec
0 means Armada 380 (singlecore), 1 means Armada 385 (dualcore) and 3
means Armada 388 (dualcore). So handling soc_num 1 and 3 the same way
is perfectly allright.

Cheers
Dirk
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Re: [U-Boot] [PATCH v0 4/5] arm: mvebu: Fix ddr3_init() cpu config

[Stefan Roese]

Hi Dirk,

On 29.10.2015 10:51, Dirk Eibach wrote:

2015-10-28 17:35 GMT+01:00 Stefan Roese :

Hi Dirk,

On 28.10.2015 16:44, dirk.eib...@gdsys.cc wrote:


From: Dirk Eibach 

Armada 38x has a maximum of two cores. Probably copy/paste
bug from Armada XP.

Signed-off-by: Dirk Eibach 
---

   drivers/ddr/marvell/a38x/ddr3_init.c | 2 --
   1 file changed, 2 deletions(-)

diff --git a/drivers/ddr/marvell/a38x/ddr3_init.c
b/drivers/ddr/marvell/a38x/ddr3_init.c
index d6ed8e0..cbfc58c 100644
--- a/drivers/ddr/marvell/a38x/ddr3_init.c
+++ b/drivers/ddr/marvell/a38x/ddr3_init.c
@@ -306,8 +306,6 @@ int ddr3_init(void)
 SAR1_CPU_CORE_OFFSET;
 switch (soc_num) {
 case 0x3:
-   reg_bit_set(CPU_CONFIGURATION_REG(3), CPU_MRVL_ID_OFFSET);
-   reg_bit_set(CPU_CONFIGURATION_REG(2), CPU_MRVL_ID_OFFSET);
 case 0x1:
 reg_bit_set(CPU_CONFIGURATION_REG(1), CPU_MRVL_ID_OFFSET);
 case 0x0:



Shouldn't you remove the "case 0x3:" line as well?


Nope, according to Reset Configuration Pins table in the hardware spec
0 means Armada 380 (singlecore), 1 means Armada 385 (dualcore) and 3
means Armada 388 (dualcore). So handling soc_num 1 and 3 the same way
is perfectly allright.


Thanks for the explanation:

Reviewed-by: Stefan Roese 

Thanks,
Stefan

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Re: [U-Boot] [PATCH v0 4/5] arm: mvebu: Fix ddr3_init() cpu config

[Stefan Roese]

Hi Dirk,

On 28.10.2015 16:44, dirk.eib...@gdsys.cc wrote:

From: Dirk Eibach 

Armada 38x has a maximum of two cores. Probably copy/paste
bug from Armada XP.

Signed-off-by: Dirk Eibach 
---

  drivers/ddr/marvell/a38x/ddr3_init.c | 2 --
  1 file changed, 2 deletions(-)

diff --git a/drivers/ddr/marvell/a38x/ddr3_init.c 
b/drivers/ddr/marvell/a38x/ddr3_init.c
index d6ed8e0..cbfc58c 100644
--- a/drivers/ddr/marvell/a38x/ddr3_init.c
+++ b/drivers/ddr/marvell/a38x/ddr3_init.c
@@ -306,8 +306,6 @@ int ddr3_init(void)
SAR1_CPU_CORE_OFFSET;
switch (soc_num) {
case 0x3:
-   reg_bit_set(CPU_CONFIGURATION_REG(3), CPU_MRVL_ID_OFFSET);
-   reg_bit_set(CPU_CONFIGURATION_REG(2), CPU_MRVL_ID_OFFSET);
case 0x1:
reg_bit_set(CPU_CONFIGURATION_REG(1), CPU_MRVL_ID_OFFSET);
case 0x0:


Shouldn't you remove the "case 0x3:" line as well?

Thanks,
Stefan

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[U-Boot] [PATCH v0 4/5] arm: mvebu: Fix ddr3_init() cpu config

[dirk . eibach]

From: Dirk Eibach 

Armada 38x has a maximum of two cores. Probably copy/paste
bug from Armada XP.

Signed-off-by: Dirk Eibach 
---

 drivers/ddr/marvell/a38x/ddr3_init.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/ddr/marvell/a38x/ddr3_init.c 
b/drivers/ddr/marvell/a38x/ddr3_init.c
index d6ed8e0..cbfc58c 100644
--- a/drivers/ddr/marvell/a38x/ddr3_init.c
+++ b/drivers/ddr/marvell/a38x/ddr3_init.c
@@ -306,8 +306,6 @@ int ddr3_init(void)
SAR1_CPU_CORE_OFFSET;
switch (soc_num) {
case 0x3:
-   reg_bit_set(CPU_CONFIGURATION_REG(3), CPU_MRVL_ID_OFFSET);
-   reg_bit_set(CPU_CONFIGURATION_REG(2), CPU_MRVL_ID_OFFSET);
case 0x1:
reg_bit_set(CPU_CONFIGURATION_REG(1), CPU_MRVL_ID_OFFSET);
case 0x0:
-- 
2.1.3

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