[U-Boot] [PATCH v10 7/9] spl : socfpga: Implement fpga bitstream loading with socfpga loadfs
From: Tien Fong Chee
Add support for loading FPGA bitstream to get DDR up running before
U-Boot is loaded into DDR. Boot device initialization, generic firmware
loader and SPL FAT support are required for this whole mechanism to work.
Signed-off-by: Tien Fong Chee
---
changes for v10
- Removed the static so the function can be referred by other c file.
changes for v9
- Used ALLOC_CACHE_ALIGN_BUFFER
- De-duplicated the same chunks of codes
changes for v7
- Removed casting for get_fpga_filename
- Removed hard coding DDR address for loading core bistream, using loadable
property from FIT.
- Added checking for config_pins, return if error.
# Conflicts:
# arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
---
.../include/mach/fpga_manager_arria10.h| 1 +
arch/arm/mach-socfpga/spl_a10.c| 31 +-
drivers/fpga/socfpga_arria10.c | 2 +-
3 files changed, 32 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
index c5f67714aa..62249b3695 100644
--- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
@@ -126,6 +126,7 @@ int fpgamgr_program_finish(void);
int is_fpgamgr_user_mode(void);
int fpgamgr_wait_early_user_mode(void);
const char *get_fpga_filename(void);
+int is_fpgamgr_early_user_mode(void);
int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
u32 offset);
void fpgamgr_program(const void *buf, size_t bsize, u32 offset);
diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
index c97eacb424..4b658c87a3 100644
--- a/arch/arm/mach-socfpga/spl_a10.c
+++ b/arch/arm/mach-socfpga/spl_a10.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2012 Altera Corporation
+ * Copyright (C) 2012-2019 Altera Corporation
*/
#include
@@ -23,6 +23,11 @@
#include
#include
#include
+#include
+#include
+#include
+
+#define FPGA_BUFSIZ16 * 1024
DECLARE_GLOBAL_DATA_PTR;
@@ -68,11 +73,35 @@ u32 spl_boot_mode(const u32 boot_device)
void spl_board_init(void)
{
+ ALLOC_CACHE_ALIGN_BUFFER(char, buf, FPGA_BUFSIZ);
+
/* enable console uart printing */
preloader_console_init();
WATCHDOG_RESET();
arch_early_init_r();
+
+ /* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */
+ if (is_fpgamgr_user_mode()) {
+ int ret = config_pins(gd->fdt_blob, "shared");
+
+ if (ret)
+ return;
+
+ ret = config_pins(gd->fdt_blob, "fpga");
+ if (ret)
+ return;
+ } else if (!is_fpgamgr_early_user_mode()) {
+ /* Program IOSSM(early IO release) or full FPGA */
+ fpgamgr_program(buf, FPGA_BUFSIZ, 0);
+ }
+
+ /* If the IOSSM/full FPGA is already loaded, start DDR */
+ if (is_fpgamgr_early_user_mode() || is_fpgamgr_user_mode())
+ ddr_calibration_sequence();
+
+ if (!is_fpgamgr_user_mode())
+ fpgamgr_program(buf, FPGA_BUFSIZ, 0);
}
void board_init_f(ulong dummy)
diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index 9df2c430d7..285280e507 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -69,7 +69,7 @@ static int wait_for_user_mode(void)
1, FPGA_TIMEOUT_MSEC, false);
}
-static int is_fpgamgr_early_user_mode(void)
+int is_fpgamgr_early_user_mode(void)
{
return (readl(_manager_base->imgcfg_stat) &
ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0;
--
2.13.0
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[U-Boot] [PATCH v10 7/9] spl : socfpga: Implement fpga bitstream loading with socfpga loadfs
From: Tien Fong Chee
Add support for loading FPGA bitstream to get DDR up running before
U-Boot is loaded into DDR. Boot device initialization, generic firmware
loader and SPL FAT support are required for this whole mechanism to work.
Signed-off-by: Tien Fong Chee
---
changes for v10
- Removed the static so the function can be referred by other c file.
changes for v9
- Used ALLOC_CACHE_ALIGN_BUFFER
- De-duplicated the same chunks of codes
changes for v7
- Removed casting for get_fpga_filename
- Removed hard coding DDR address for loading core bistream, using loadable
property from FIT.
- Added checking for config_pins, return if error.
# Conflicts:
# arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
---
.../include/mach/fpga_manager_arria10.h| 1 +
arch/arm/mach-socfpga/spl_a10.c| 31 +-
drivers/fpga/socfpga_arria10.c | 2 +-
3 files changed, 32 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
index c5f67714aa..62249b3695 100644
--- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
@@ -126,6 +126,7 @@ int fpgamgr_program_finish(void);
int is_fpgamgr_user_mode(void);
int fpgamgr_wait_early_user_mode(void);
const char *get_fpga_filename(void);
+int is_fpgamgr_early_user_mode(void);
int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
u32 offset);
void fpgamgr_program(const void *buf, size_t bsize, u32 offset);
diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
index c97eacb424..4b658c87a3 100644
--- a/arch/arm/mach-socfpga/spl_a10.c
+++ b/arch/arm/mach-socfpga/spl_a10.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2012 Altera Corporation
+ * Copyright (C) 2012-2019 Altera Corporation
*/
#include
@@ -23,6 +23,11 @@
#include
#include
#include
+#include
+#include
+#include
+
+#define FPGA_BUFSIZ16 * 1024
DECLARE_GLOBAL_DATA_PTR;
@@ -68,11 +73,35 @@ u32 spl_boot_mode(const u32 boot_device)
void spl_board_init(void)
{
+ ALLOC_CACHE_ALIGN_BUFFER(char, buf, FPGA_BUFSIZ);
+
/* enable console uart printing */
preloader_console_init();
WATCHDOG_RESET();
arch_early_init_r();
+
+ /* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */
+ if (is_fpgamgr_user_mode()) {
+ int ret = config_pins(gd->fdt_blob, "shared");
+
+ if (ret)
+ return;
+
+ ret = config_pins(gd->fdt_blob, "fpga");
+ if (ret)
+ return;
+ } else if (!is_fpgamgr_early_user_mode()) {
+ /* Program IOSSM(early IO release) or full FPGA */
+ fpgamgr_program(buf, FPGA_BUFSIZ, 0);
+ }
+
+ /* If the IOSSM/full FPGA is already loaded, start DDR */
+ if (is_fpgamgr_early_user_mode() || is_fpgamgr_user_mode())
+ ddr_calibration_sequence();
+
+ if (!is_fpgamgr_user_mode())
+ fpgamgr_program(buf, FPGA_BUFSIZ, 0);
}
void board_init_f(ulong dummy)
diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index 9df2c430d7..285280e507 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -69,7 +69,7 @@ static int wait_for_user_mode(void)
1, FPGA_TIMEOUT_MSEC, false);
}
-static int is_fpgamgr_early_user_mode(void)
+int is_fpgamgr_early_user_mode(void)
{
return (readl(_manager_base->imgcfg_stat) &
ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0;
--
2.13.0
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