[U-Boot] [PATCH v2] exynos5250/arndale: Enable SATA/AHCI support.
This is based on some old patches from the chromeos-v2011.12 branch of
http://git.chromium.org/chromiumos/third_party/u-boot.git by Taylor Hutt.
Specifically:
http://git.chromium.org/gitweb/?p=chromiumos/third_party/u-boot.git;a=commit;h=26f6c570b5deb37c52306920ae049203c68f014a
exynos: sata: on-board controller initialization
Signed-off-by: Taylor Hutt th...@chromium.org
http://git.chromium.org/gitweb/?p=chromiumos/third_party/u-boot.git;a=commit;h=d8cac5cf0b63df00d2d6ac7df814613e4b60b9d1
exynos: sata: Add sata_initialize() interface
Signed-off-by: Taylor Hutt th...@chromium.org
http://git.chromium.org/gitweb/?p=chromiumos/third_party/u-boot.git;a=commit;h=dd32462453d6328bc5770859d1b56501f7920d7d
exynos: sata: SATA self-configuration for when SATA device is enabled
Signed-off-by: Taylor Hutt th...@chromium.org
As well as rebasing there have been some significant changes.
- Drop support for smdk5250, which I don't own.
- Implement support for arndale, which I do.
- Since arndale has no need to frob a GPIO on SATA init drop the associated
code.
- Initialise via the existing scsi_init hook rather than introducing
sata_initialize, associated build system and include/configs/*.h changes.
- Use set/clrbits in a bunch of places
- Add some #defines for some magic numbers.
- Use samsung_get_base_* for peripheral base addresses and structs to
access individual registers
- Lots of coding style improvements (checkpatch.pl clean) and general cleanup
Before launching the OS reset the PHY, otherwise Linux cannot reliably
detect the disk.
Signed-off-by: Ian Campbell ian.campb...@citrix.com
Cc: Taylor Hutt th...@chromium.org
Cc: Simon Glass s...@chromium.org
---
Lots of changes in v2:
- Rebase to latest master branch.
- use samsung_get_base_* for sata phy
- use samsung_get_base_* for sata i2c
- use samsung_get_base_* for sata axi
- Lots of Coding Style improvements
- Drop unused mmio argument to phy init
- Move code controlling phy power to power.c
- Remove unused SCLK_SATA_FREQ
- Use #defines for SATA_GENERATIONN, less fickle than enum
- avoid non-existent BIT macro
- Use bool more consistently in a few places
- No uppercase variable names
- Use SPDX License + copyright
- Use arch_preboot_os to reset SATA controller, and do so more
thoroughly than in the previous HACK. It now appears to be reliable
in my testing.
---
arch/arm/cpu/armv7/exynos/Makefile | 4 +
arch/arm/cpu/armv7/exynos/power.c| 23 ++
arch/arm/cpu/armv7/exynos/sata.c | 412 +++
arch/arm/cpu/armv7/exynos/soc.c | 8 +
arch/arm/include/asm/arch-exynos/cpu.h | 15 ++
arch/arm/include/asm/arch-exynos/power.h | 4 +
arch/arm/include/asm/arch-exynos/sata.h | 13 +
arch/arm/lib/board.c | 1 +
board/samsung/arndale/arndale.c | 9 +
include/configs/arndale.h| 3 +
include/configs/exynos5-common.h | 18 ++
11 files changed, 510 insertions(+)
create mode 100644 arch/arm/cpu/armv7/exynos/sata.c
create mode 100644 arch/arm/include/asm/arch-exynos/sata.h
diff --git a/arch/arm/cpu/armv7/exynos/Makefile
b/arch/arm/cpu/armv7/exynos/Makefile
index e207bd6..c74a2d4 100644
--- a/arch/arm/cpu/armv7/exynos/Makefile
+++ b/arch/arm/cpu/armv7/exynos/Makefile
@@ -7,6 +7,10 @@
obj-y += clock.o power.o soc.o system.o pinmux.o tzpc.o
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_EXYNOS5250_AHCI) += sata.o
+endif
+
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_EXYNOS5) += clock_init_exynos5.o
obj-$(CONFIG_EXYNOS5) += dmc_common.o dmc_init_ddr3.o
diff --git a/arch/arm/cpu/armv7/exynos/power.c
b/arch/arm/cpu/armv7/exynos/power.c
index 1520d64..8f36d10 100644
--- a/arch/arm/cpu/armv7/exynos/power.c
+++ b/arch/arm/cpu/armv7/exynos/power.c
@@ -37,6 +37,29 @@ void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int
enable)
exynos4_mipi_phy_control(dev_index, enable);
}
+void exynos5_set_sata_phy_ctrl(unsigned int enable)
+{
+ struct exynos5_power *power =
+ (struct exynos5_power *)samsung_get_base_power();
+
+ if (enable) {
+ /* Enabling SATA_PHY */
+ setbits_le32(power-sata_phy_control,
+POWER_USB_HOST_PHY_CTRL_EN);
+ } else {
+ /* Disabling SATA_PHY */
+ clrbits_le32(power-sata_phy_control,
+POWER_USB_HOST_PHY_CTRL_EN);
+ }
+}
+
+void set_sata_phy_ctrl(unsigned int enable)
+{
+ if (cpu_is_exynos5())
+ exynos5_set_sata_phy_ctrl(enable);
+}
+
+
void exynos5_set_usbhost_phy_ctrl(unsigned int enable)
{
struct exynos5_power *power =
diff --git a/arch/arm/cpu/armv7/exynos/sata.c b/arch/arm/cpu/armv7/exynos/sata.c
new file mode 100644
index 000..4e994d6
--- /dev/null
+++ b/arch/arm/cpu/armv7/exynos/sata.c
@@ -0,0 +1,412 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ * Copyright (c) 2014 Ian Campbell
+ *
+
Re: [U-Boot] [PATCH v2] exynos5250/arndale: Enable SATA/AHCI support.
Hi Ian,
On 8 December 2014 at 07:54, Ian Campbell ian.campb...@citrix.com wrote:
This is based on some old patches from the chromeos-v2011.12 branch of
http://git.chromium.org/chromiumos/third_party/u-boot.git by Taylor Hutt.
Specifically:
http://git.chromium.org/gitweb/?p=chromiumos/third_party/u-boot.git;a=commit;h=26f6c570b5deb37c52306920ae049203c68f014a
exynos: sata: on-board controller initialization
Signed-off-by: Taylor Hutt th...@chromium.org
http://git.chromium.org/gitweb/?p=chromiumos/third_party/u-boot.git;a=commit;h=d8cac5cf0b63df00d2d6ac7df814613e4b60b9d1
exynos: sata: Add sata_initialize() interface
Signed-off-by: Taylor Hutt th...@chromium.org
http://git.chromium.org/gitweb/?p=chromiumos/third_party/u-boot.git;a=commit;h=dd32462453d6328bc5770859d1b56501f7920d7d
exynos: sata: SATA self-configuration for when SATA device is enabled
Signed-off-by: Taylor Hutt th...@chromium.org
Thanks for cleaning this up and submitting it.
As well as rebasing there have been some significant changes.
- Drop support for smdk5250, which I don't own.
- Implement support for arndale, which I do.
- Since arndale has no need to frob a GPIO on SATA init drop the associated
code.
- Initialise via the existing scsi_init hook rather than introducing
sata_initialize, associated build system and include/configs/*.h changes.
- Use set/clrbits in a bunch of places
- Add some #defines for some magic numbers.
- Use samsung_get_base_* for peripheral base addresses and structs to
access individual registers
- Lots of coding style improvements (checkpatch.pl clean) and general cleanup
Before launching the OS reset the PHY, otherwise Linux cannot reliably
detect the disk.
Signed-off-by: Ian Campbell ian.campb...@citrix.com
Cc: Taylor Hutt th...@chromium.org
Cc: Simon Glass s...@chromium.org
---
Lots of changes in v2:
- Rebase to latest master branch.
- use samsung_get_base_* for sata phy
- use samsung_get_base_* for sata i2c
- use samsung_get_base_* for sata axi
- Lots of Coding Style improvements
- Drop unused mmio argument to phy init
- Move code controlling phy power to power.c
- Remove unused SCLK_SATA_FREQ
- Use #defines for SATA_GENERATIONN, less fickle than enum
- avoid non-existent BIT macro
- Use bool more consistently in a few places
- No uppercase variable names
- Use SPDX License + copyright
- Use arch_preboot_os to reset SATA controller, and do so more
thoroughly than in the previous HACK. It now appears to be reliable
in my testing.
---
arch/arm/cpu/armv7/exynos/Makefile | 4 +
arch/arm/cpu/armv7/exynos/power.c| 23 ++
arch/arm/cpu/armv7/exynos/sata.c | 412
+++
arch/arm/cpu/armv7/exynos/soc.c | 8 +
arch/arm/include/asm/arch-exynos/cpu.h | 15 ++
arch/arm/include/asm/arch-exynos/power.h | 4 +
arch/arm/include/asm/arch-exynos/sata.h | 13 +
arch/arm/lib/board.c | 1 +
board/samsung/arndale/arndale.c | 9 +
include/configs/arndale.h| 3 +
include/configs/exynos5-common.h | 18 ++
11 files changed, 510 insertions(+)
create mode 100644 arch/arm/cpu/armv7/exynos/sata.c
create mode 100644 arch/arm/include/asm/arch-exynos/sata.h
diff --git a/arch/arm/cpu/armv7/exynos/Makefile
b/arch/arm/cpu/armv7/exynos/Makefile
index e207bd6..c74a2d4 100644
--- a/arch/arm/cpu/armv7/exynos/Makefile
+++ b/arch/arm/cpu/armv7/exynos/Makefile
@@ -7,6 +7,10 @@
obj-y += clock.o power.o soc.o system.o pinmux.o tzpc.o
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_EXYNOS5250_AHCI) += sata.o
+endif
+
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_EXYNOS5) += clock_init_exynos5.o
obj-$(CONFIG_EXYNOS5) += dmc_common.o dmc_init_ddr3.o
diff --git a/arch/arm/cpu/armv7/exynos/power.c
b/arch/arm/cpu/armv7/exynos/power.c
index 1520d64..8f36d10 100644
--- a/arch/arm/cpu/armv7/exynos/power.c
+++ b/arch/arm/cpu/armv7/exynos/power.c
@@ -37,6 +37,29 @@ void set_mipi_phy_ctrl(unsigned int dev_index, unsigned
int enable)
exynos4_mipi_phy_control(dev_index, enable);
}
+void exynos5_set_sata_phy_ctrl(unsigned int enable)
+{
+ struct exynos5_power *power =
+ (struct exynos5_power *)samsung_get_base_power();
+
+ if (enable) {
+ /* Enabling SATA_PHY */
+ setbits_le32(power-sata_phy_control,
+POWER_USB_HOST_PHY_CTRL_EN);
+ } else {
+ /* Disabling SATA_PHY */
+ clrbits_le32(power-sata_phy_control,
+POWER_USB_HOST_PHY_CTRL_EN);
+ }
+}
+
+void set_sata_phy_ctrl(unsigned int enable)
+{
+ if (cpu_is_exynos5())
+ exynos5_set_sata_phy_ctrl(enable);
+}
+
+
void exynos5_set_usbhost_phy_ctrl(unsigned int enable)
{
struct exynos5_power *power =
diff --git a/arch/arm/cpu/armv7/exynos/sata.c
