Re: [U-Boot] [PATCH v2] mx6: clock: Fix the calculation of PLL_ENET frequency

2013-12-17 Thread Stefano Babic
On 03/12/2013 21:26, Fabio Estevam wrote:
> From: Fabio Estevam 
> 
> According to the mx6 quad reference manual, the DIV_SELECT field of register
> CCM_ANALOG_PLL_ENETn has the following meaning:
> 
> "Controls the frequency of the ethernet reference clock.
> - 00 - 25MHz
> - 01 - 50MHz
> - 10 - 100MHz
> - 11 - 125MHz"
> 
> Current logic does not handle the 25MHz case correctly, so fix it.
> 
> Signed-off-by: Rabeeh Khoury 
> Signed-off-by: Fabio Estevam 
> ---

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic



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[U-Boot] [PATCH v2] mx6: clock: Fix the calculation of PLL_ENET frequency

2013-12-03 Thread Fabio Estevam
From: Fabio Estevam 

According to the mx6 quad reference manual, the DIV_SELECT field of register
CCM_ANALOG_PLL_ENETn has the following meaning:

"Controls the frequency of the ethernet reference clock.
- 00 - 25MHz
- 01 - 50MHz
- 10 - 100MHz
- 11 - 125MHz"

Current logic does not handle the 25MHz case correctly, so fix it.

Signed-off-by: Rabeeh Khoury 
Signed-off-by: Fabio Estevam 
---
Changes since v1:
- Use a single expression that correctly computes the frequency for all
the DIV_SELECT combination (Troy Kisky)

 arch/arm/cpu/armv7/mx6/clock.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 873d9d0..20c7e70 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -94,7 +94,7 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq)
div = __raw_readl(&imx_ccm->analog_pll_enet);
div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
 
-   return (div == 3 ? 12500 : 2500 * (div << 1));
+   return 2500 * (div + (div >> 1) + 1);
default:
return 0;
}
-- 
1.8.1.2

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