Re: [U-Boot] [PATCH v2] powerpc/mpc83xx: set TXEQA/TXEQE value for mpc837XE sata
On Sun, 11 Dec 2011 21:26:34 -0600 Huang Changming-R66093 r66...@freescale.com wrote: From: Huang Changming-R66093 Sent: Thursday, November 17, 2011 10:16 AM In the current u-boot code, the value of these fields are the reserved value (0b100), through the signal integrity measurement on freescale's board with these reserved setting, the signal eye is out of the recommended spec for non-transition amplitude at 500mV nominal. According to the errata for MPC8379E, we should make a change to the recommended setting from essentially nothing at this time to 0b001 for SATA. Signed-off-by: Jerry Huang chang-ming.hu...@freescale.com CC: Kim Phillips kim.phill...@freescale.com --- changes for v2: - use clrsetbits_be32 to clear and set the value applied to 83xx/master, thanks. Kim ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] powerpc/mpc83xx: set TXEQA/TXEQE value for mpc837XE sata
Hi, Kim Do you have any comment on this patch? -Original Message- From: Huang Changming-R66093 Sent: Thursday, November 17, 2011 10:16 AM To: u-boot@lists.denx.de Cc: Huang Changming-R66093; Phillips Kim-R1AAHA Subject: [PATCH v2] powerpc/mpc83xx: set TXEQA/TXEQE value for mpc837XE sata From: Jerry Huang chang-ming.hu...@freescale.com In the current u-boot code, the value of these fields are the reserved value (0b100), through the signal integrity measurement on freescale's board with these reserved setting, the signal eye is out of the recommended spec for non-transition amplitude at 500mV nominal. According to the errata for MPC8379E, we should make a change to the recommended setting from essentially nothing at this time to 0b001 for SATA. Signed-off-by: Jerry Huang chang-ming.hu...@freescale.com CC: Kim Phillips kim.phill...@freescale.com --- changes for v2: - use clrsetbits_be32 to clear and set the value arch/powerpc/cpu/mpc83xx/serdes.c | 11 ++- 1 files changed, 10 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/serdes.c b/arch/powerpc/cpu/mpc83xx/serdes.c index fecfc80..a88fab9 100644 --- a/arch/powerpc/cpu/mpc83xx/serdes.c +++ b/arch/powerpc/cpu/mpc83xx/serdes.c @@ -1,7 +1,7 @@ /* * Freescale SerDes initialization routine * - * Copyright (C) 2007 Freescale Semicondutor, Inc. + * Copyright (C) 2007,2011 Freescale Semicondutor, Inc. * Copyright (C) 2008 MontaVista Software, Inc. * * Author: Li Yang le...@freescale.com @@ -20,6 +20,10 @@ /* SerDes registers */ #define FSL_SRDSCR0_OFFS 0x0 #define FSL_SRDSCR0_DPP_1V2 0x8800 +#define FSL_SRDSCR0_TXEQA_MASK 0x7000 +#define FSL_SRDSCR0_TXEQA_SATA 0x1000 +#define FSL_SRDSCR0_TXEQE_MASK 0x0700 +#define FSL_SRDSCR0_TXEQE_SATA 0x0100 #define FSL_SRDSCR1_OFFS 0x4 #define FSL_SRDSCR1_PLLBW0x0040 #define FSL_SRDSCR2_OFFS 0x8 @@ -71,6 +75,11 @@ void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd) tmp = ~FSL_SRDSRSTCTL_SATA_RESET; out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp); + /* Configure SRDSCR0 */ + clrsetbits_be32(regs + FSL_SRDSCR0_OFFS, + FSL_SRDSCR0_TXEQA_MASK | FSL_SRDSCR0_TXEQE_MASK, + FSL_SRDSCR0_TXEQA_SATA | FSL_SRDSCR0_TXEQE_SATA); + /* Configure SRDSCR1 */ tmp = in_be32(regs + FSL_SRDSCR1_OFFS); tmp = ~FSL_SRDSCR1_PLLBW; -- 1.6.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] powerpc/mpc83xx: set TXEQA/TXEQE value for mpc837XE sata
From: Jerry Huang chang-ming.hu...@freescale.com In the current u-boot code, the value of these fields are the reserved value (0b100), through the signal integrity measurement on freescale's board with these reserved setting, the signal eye is out of the recommended spec for non-transition amplitude at 500mV nominal. According to the errata for MPC8379E, we should make a change to the recommended setting from essentially nothing at this time to 0b001 for SATA. Signed-off-by: Jerry Huang chang-ming.hu...@freescale.com CC: Kim Phillips kim.phill...@freescale.com --- changes for v2: - use clrsetbits_be32 to clear and set the value arch/powerpc/cpu/mpc83xx/serdes.c | 11 ++- 1 files changed, 10 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/serdes.c b/arch/powerpc/cpu/mpc83xx/serdes.c index fecfc80..a88fab9 100644 --- a/arch/powerpc/cpu/mpc83xx/serdes.c +++ b/arch/powerpc/cpu/mpc83xx/serdes.c @@ -1,7 +1,7 @@ /* * Freescale SerDes initialization routine * - * Copyright (C) 2007 Freescale Semicondutor, Inc. + * Copyright (C) 2007,2011 Freescale Semicondutor, Inc. * Copyright (C) 2008 MontaVista Software, Inc. * * Author: Li Yang le...@freescale.com @@ -20,6 +20,10 @@ /* SerDes registers */ #define FSL_SRDSCR0_OFFS 0x0 #define FSL_SRDSCR0_DPP_1V20x8800 +#define FSL_SRDSCR0_TXEQA_MASK 0x7000 +#define FSL_SRDSCR0_TXEQA_SATA 0x1000 +#define FSL_SRDSCR0_TXEQE_MASK 0x0700 +#define FSL_SRDSCR0_TXEQE_SATA 0x0100 #define FSL_SRDSCR1_OFFS 0x4 #define FSL_SRDSCR1_PLLBW 0x0040 #define FSL_SRDSCR2_OFFS 0x8 @@ -71,6 +75,11 @@ void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd) tmp = ~FSL_SRDSRSTCTL_SATA_RESET; out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp); + /* Configure SRDSCR0 */ + clrsetbits_be32(regs + FSL_SRDSCR0_OFFS, + FSL_SRDSCR0_TXEQA_MASK | FSL_SRDSCR0_TXEQE_MASK, + FSL_SRDSCR0_TXEQA_SATA | FSL_SRDSCR0_TXEQE_SATA); + /* Configure SRDSCR1 */ tmp = in_be32(regs + FSL_SRDSCR1_OFFS); tmp = ~FSL_SRDSCR1_PLLBW; -- 1.6.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
