[U-Boot] [PATCH v2] sh: add support for sh7757lcr board
The R0P7757LC0030RL board has SH7757, 256MB DDR3-SDRAM, SPI ROM,
Ethernet, and more.
This patch supports the following functions:
- 256MB DDR3-SDRAM
- SPI ROM
- Ethernet
Signed-off-by: Yoshihiro Shimoda
---
about v2:
- add MAINTAINERS
- remove config.mk of this board
- modify lowlevel_init.S
- remove unuse hardware registers on C source in cpu_sh7757.h
- change hardware registers to C structure
- fix some coding style
(This patch depends on "sh: add support the CONFIG_SYS_LDSCRIPT")
MAINTAINERS |1 +
arch/sh/include/asm/cpu_sh4.h |2 +
arch/sh/include/asm/cpu_sh7757.h| 218
board/renesas/sh7757lcr/Makefile| 43 +++
board/renesas/sh7757lcr/lowlevel_init.S | 558 +++
board/renesas/sh7757lcr/sh7757lcr.c | 454 +
board/renesas/sh7757lcr/spi-boot.c | 109 ++
board/renesas/sh7757lcr/u-boot.lds | 101 ++
boards.cfg |1 +
doc/README.sh7757lcr| 64
include/configs/sh7757lcr.h | 146
11 files changed, 1697 insertions(+), 0 deletions(-)
create mode 100644 arch/sh/include/asm/cpu_sh7757.h
create mode 100644 board/renesas/sh7757lcr/Makefile
create mode 100644 board/renesas/sh7757lcr/lowlevel_init.S
create mode 100644 board/renesas/sh7757lcr/sh7757lcr.c
create mode 100644 board/renesas/sh7757lcr/spi-boot.c
create mode 100644 board/renesas/sh7757lcr/u-boot.lds
create mode 100644 doc/README.sh7757lcr
create mode 100644 include/configs/sh7757lcr.h
diff --git a/MAINTAINERS b/MAINTAINERS
index d7cd09c..7313542 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1020,6 +1020,7 @@ Mark Jonas
Yoshihiro Shimoda
MS7720SESH7720
+ R0P77570030RL SH7757
R0P77850011RL SH7785
#
diff --git a/arch/sh/include/asm/cpu_sh4.h b/arch/sh/include/asm/cpu_sh4.h
index fdcebd6..9b29d3a 100644
--- a/arch/sh/include/asm/cpu_sh4.h
+++ b/arch/sh/include/asm/cpu_sh4.h
@@ -44,6 +44,8 @@
# include
#elif defined (CONFIG_CPU_SH7723)
# include
+#elif defined (CONFIG_CPU_SH7757)
+# include
#elif defined (CONFIG_CPU_SH7763)
# include
#elif defined (CONFIG_CPU_SH7780)
diff --git a/arch/sh/include/asm/cpu_sh7757.h b/arch/sh/include/asm/cpu_sh7757.h
new file mode 100644
index 000..17a6537
--- /dev/null
+++ b/arch/sh/include/asm/cpu_sh7757.h
@@ -0,0 +1,218 @@
+/*
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_CPU_SH7757_H_
+#define _ASM_CPU_SH7757_H_
+
+#define CCR0xFF1C
+#define WTCNT 0xFFCC
+#define CCR_CACHE_INIT 0x090b
+#define CACHE_OC_NUM_WAYS 1
+
+#ifndef __ASSEMBLY__ /* put C only stuff in this section */
+/* MMU */
+struct mmu_regs {
+ unsigned intreserved[4];
+ unsigned intmmucr;
+};
+#define MMU_BASE ((struct mmu_regs *)0xff00)
+
+/* Watchdog */
+#define WTCSR0 0xffcc0002
+#define WRSTCSR_R 0xffcc0003
+#define WRSTCSR_W 0xffcc0002
+#define WTCSR_PREFIX 0xa500
+#define WRSTCSR_PREFIX 0x6900
+#define WRSTCSR_WOVF_PREFIX0x9600
+
+/* SCIF */
+#define SCIF0_BASE 0xfe4b /* The real name is SCIF2 */
+#define SCIF1_BASE 0xfe4c /* The real name is SCIF3 */
+#define SCIF2_BASE 0xfe4d /* The real name is SCIF4 */
+
+/* SerMux */
+#define SMR0 0xfe47
+
+/* TMU0 */
+#define TSTR 0xFE430004
+#define TOCR 0xFE43
+#define TSTR0 0xFE430004
+#define TCOR0 0xFE430008
+#define TCNT0 0xFE43000C
+#define TCR0 0xFE430010
+#define TCOR1 0xFE430014
+#define TCNT1 0xFE430018
+#define TCR1 0xFE43001C
+#define TCOR2 0xFE430020
+#define TCNT2 0xFE430024
+#define TCR2 0xFE430028
+#define TCPR2 0xFE43002C
+
+/* ETHER, GETHER MAC address */
+struct ether_mac_regs {
+ unsigned intreserved[114];
+ unsigned intmahr;
+ unsigned intreserved2;
+ unsigned intmalr;
+};
+#define GETHER0_MAC_BASE ((struct ether_mac_regs *)0xfee040
[U-Boot] [PATCH v2] sh: add support for sh7757lcr board
The R0P7757LC0030RL board has SH7757, 256MB DDR3-SDRAM, SPI ROM, Ethernet, and more. This patch supports the following functions: - 256MB DDR3-SDRAM - SPI ROM - Ethernet Signed-off-by: Yoshihiro Shimoda --- about v2: - remove unnecessary comment in config.mk - move CONFIG_SYS_TEXT_BASE to include/configs/sh7757lcr.h - replace local parse function with eth_parse_enetaddr() - add NULL checking for malloc. - update copyright in u-boot.lds arch/sh/include/asm/cpu_sh4.h |2 + arch/sh/include/asm/cpu_sh7757.h| 263 +++ board/renesas/sh7757lcr/Makefile| 42 +++ board/renesas/sh7757lcr/config.mk | 26 ++ board/renesas/sh7757lcr/lowlevel_init.S | 558 +++ board/renesas/sh7757lcr/sh7757lcr.c | 432 board/renesas/sh7757lcr/spi-boot.c | 111 ++ board/renesas/sh7757lcr/u-boot.lds | 101 ++ boards.cfg |1 + doc/README.sh7757lcr| 64 include/configs/sh7757lcr.h | 145 11 files changed, 1745 insertions(+), 0 deletions(-) create mode 100644 arch/sh/include/asm/cpu_sh7757.h create mode 100644 board/renesas/sh7757lcr/Makefile create mode 100644 board/renesas/sh7757lcr/config.mk create mode 100644 board/renesas/sh7757lcr/lowlevel_init.S create mode 100644 board/renesas/sh7757lcr/sh7757lcr.c create mode 100644 board/renesas/sh7757lcr/spi-boot.c create mode 100644 board/renesas/sh7757lcr/u-boot.lds create mode 100644 doc/README.sh7757lcr create mode 100644 include/configs/sh7757lcr.h diff --git a/arch/sh/include/asm/cpu_sh4.h b/arch/sh/include/asm/cpu_sh4.h index fdcebd6..9b29d3a 100644 --- a/arch/sh/include/asm/cpu_sh4.h +++ b/arch/sh/include/asm/cpu_sh4.h @@ -44,6 +44,8 @@ # include #elif defined (CONFIG_CPU_SH7723) # include +#elif defined (CONFIG_CPU_SH7757) +# include #elif defined (CONFIG_CPU_SH7763) # include #elif defined (CONFIG_CPU_SH7780) diff --git a/arch/sh/include/asm/cpu_sh7757.h b/arch/sh/include/asm/cpu_sh7757.h new file mode 100644 index 000..eb9ff5b --- /dev/null +++ b/arch/sh/include/asm/cpu_sh7757.h @@ -0,0 +1,263 @@ +/* + * Copyright (C) 2009 Renesas Solutions Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ASM_CPU_SH7757_H_ +#define _ASM_CPU_SH7757_H_ + +#define CCR0xFF1C +#define WTCNT 0xFFCC +#define CCR_CACHE_INIT 0x090b +#defineCACHE_OC_NUM_WAYS 1 + +/* Exception */ +#define EXPEVT 0xff24 +#define INTEVT 0xff28 + +/* Watchdog */ +#define WTCSR0 0xffcc0002 +#define WRSTCSR_R 0xffcc0003 +#define WRSTCSR_W 0xffcc0002 +#define WTCSR_PREFIX 0xa500 +#define WRSTCSR_PREFIX 0x6900 +#define WRSTCSR_WOVF_PREFIX0x9600 + + +/* SCIF */ +#define SCIF0_BASE 0xfe4b /* The real name is SCIF2 */ +#define SCIF1_BASE 0xfe4c /* The real name is SCIF3 */ +#define SCIF2_BASE 0xfe4d /* The real name is SCIF4 */ + +/* SerMux */ +#define SMR0 0xfe47 + +/* TMU0 */ +#define TSTR 0xFE430004 +#define TOCR 0xFE43 +#define TSTR0 0xFE430004 +#define TCOR0 0xFE430008 +#define TCNT0 0xFE43000C +#define TCR0 0xFE430010 +#define TCOR1 0xFE430014 +#define TCNT1 0xFE430018 +#define TCR1 0xFE43001C +#define TCOR2 0xFE430020 +#define TCNT2 0xFE430024 +#define TCR2 0xFE430028 +#define TCPR2 0xFE43002C + +/* BSC */ +#define BCR0xFE801000 +#define CS0BCR 0xFF802000 +#define CS0WCR 0xFF802008 +#define CS4BCR 0xFF802040 +#define CS4WCR 0xFF802048 +#define CS5BCR 0xFF802050 +#define CS5WCR 0xFF802058 +#define CS6BCR 0xFF802060 +#define CS6WCR 0xFF802068 + +/* DDR3IF */ +#define DDR3IF_BASE0xfe80 +#define DBSTATE0 (DDR3IF_BASE + 0x0008) +#define DBSTATE1 (DDR3IF_BASE + 0x000c) +#define DBACEN (DDR3IF_BASE + 0x0010) +#define DBRFEN (DDR3IF_BASE + 0x0014) +#define DBCMD (DDR3IF_BASE + 0x0018) +#define DBWAIT (DDR3IF_BASE + 0x001c) +#define DBKIND (DDR3IF_BASE + 0x0020) +#define DBC
